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1.发明申请公开(公告)号：US20140376305A1
公开(公告)日：2014-12-25
申请号：US14369651
申请日：2012-12-27
Applicant: SOUTHEAST UNIVERSITY
Inventor： Na Bai , Longxing Shi , Jun Yang , Xinning Liu , Jiafeng Zhu , Yue Feng , Cai Gong , Fei Pan , Hong Chang , Yifeng Deng , Yuan Chen , Yingcheng Xia
IPC: G11C11/419 , H01L27/11
CPC classification number: G11C11/419 , G11C11/412 , G11C11/417 , H01L27/1104
Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes. The circuit improves the noise margin of sub-threshold SRAM memory cells and effectively improves the process robustness of sub-threshold SRAM memory cells.
Abstract translation: 本发明公开了一种用于提高亚阈值SRAM存储单元的处理鲁棒性的电路，其用作子阈值SRAM存储单元的辅助电路。 电路的输出连接到子阈值SRAM存储单元的PMOS管和电路中的PMOS管的衬底。 该电路包括用于PMOS管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS管和NMOS管的阈值电压波动，以自适应方式改变子阈值SRAM存储单元中的PMOS管的衬底电压和电路中的PMOS管的衬底电压 从而调节PMOS管的阈值电压，使得PMOS管的阈值电压与NMOS管的阈值电压相匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限，有效提高了亚阈值SRAM存储单元的工艺稳健性。
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公开(公告)号：US11190140B2
公开(公告)日：2021-11-30
申请号：US16967745
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao Chen , Jun Yang , Xinning Liu
Abstract: A wide voltage trans-impedance amplifier includes a first P-channel metal oxide semiconductor (PMOS) transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3, a first N-channel metal oxide semiconductor (NMOS) transistor NM1, and a second NMOS transistor NM2. A common-gate amplifier detects a change of an input voltage, and a negative feedback is constructed by injecting a current into a current mirror to achieve a low input impedance. The trans-impedance amplifier uses a common-gate amplifier to monitor an input voltage and uses a current mirror to perform the transconductance enhancement on an input transistor, while ensuring a relatively high loop gain.
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公开(公告)号：US11290009B2
公开(公告)日：2022-03-29
申请号：US16966474
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao Chen , Jun Yang , Xinning Liu
Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.
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公开(公告)号：US09236115B2
公开(公告)日：2016-01-12
申请号：US14369651
申请日：2012-12-27
Applicant: SOUTHEAST UNIVERSITY
Inventor： Na Bai , Longxing Shi , Jun Yang , Xinning Liu , Jiafeng Zhu , Yue Feng , Cai Gong , Fei Pan , Hong Chang , Yifeng Deng , Yuan Chen , Yingcheng Xia
IPC: G11C11/419 , G11C11/417 , H01L27/11 , G11C11/412
CPC classification number: G11C11/419 , G11C11/412 , G11C11/417 , H01L27/1104
Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.
Abstract translation: 用于提高子阈值SRAM存储单元的工艺稳健性的电路用作子阈值SRAM存储单元的辅助电路。 电路的输出端连接到子阈值SRAM存储单元的PMOS晶体管和电路中PMOS晶体管的衬底。 该电路包括用于PMOS晶体管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS和NMOS晶体管的阈值电压波动，以自适应的方式改变子阈值SRAM存储单元中的PMOS晶体管的衬底电压和电路中的PMOS晶体管，从而调节阈值 PMOS晶体管的电压，使得PMOS和NMOS晶体管的阈值电压匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限和子阈值SRAM存储单元的工艺稳健性。
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Patent Agency Ranking
公开(公告)号：US08922265B1
公开(公告)日：2014-12-30
申请号：US14369652
申请日：2012-12-27
Applicant: Southeast University
Inventor： Na Bai , Longxing Shi , Jun Yang , Xinning Liu , Jiafeng Zhu , Yue Feng , Cai Gong , Fei Pan , Hong Chang , Yifeng Deng , Yuan Chen , Yingcheng Xia
CPC classification number: H03K3/013 , G11C11/417 , G11C11/419 , H03K3/012
Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.
Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。
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公开(公告)号：US11196335B2
公开(公告)日：2021-12-07
申请号：US16968594
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao Chen , Jun Yang , Xinning Liu
Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.
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公开(公告)号：US11175686B2
公开(公告)日：2021-11-16
申请号：US16966476
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao Chen , Jun Yang , Xinning Liu
Abstract: A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.
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公开(公告)号：US10422883B2
公开(公告)日：2019-09-24
申请号：US16309939
申请日：2016-06-27
Applicant: Southeast University
Inventor： Yuan Zhuang , Jinfeng Ma , Longning Qi , Xinning Liu , Jun Yang
Abstract: A positioning method using height-constraint-based extended Kalman filter, suitable for a GNSS navigation and positioning system, comprises: obtaining an estimated state value of a current epoch by using an extended Kalman filter algorithm and according to an estimated state value of a previous epoch; constraining a positioning height of the current epoch by establishing a height constraint condition, so as to obtain an optimum estimated value of the current epoch and a corresponding mean square error, wherein the optimum estimated value satisfies the height constraint condition; further correcting the estimated state value by using a pseudorange obtained from the mean square error and a measured Doppler shift residual to obtain a final estimated state value of the current epoch, thus more accurately obtaining positioning information of a target to be positioned in the current epoch and enhancing the accuracy of GNSS navigation and positioning.
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公开(公告)号：US20150008971A1
公开(公告)日：2015-01-08
申请号：US14369652
申请日：2012-12-27
Applicant: SOUTHEAST UNIVERSITY
Inventor： Na Bai , Longxing Shi , Jun Yang , Xinning Liu , Jiafeng Zhu , Yue Feng , Cai Gong , Fei Pan , Hong Chang , Yifeng Deng , Yuan Chen , Yingcheng Xia
CPC classification number: H03K3/013 , G11C11/417 , G11C11/419 , H03K3/012
Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.
Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。
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