公开(公告)号：US20220020816A1

公开(公告)日：2022-01-20

申请号：US17489425

申请日：2021-09-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe BOIVIN ,  Jean Jacques FAGOT ,  Emmanuel PETITPREZ ,  Emeline SOUCHIER ,  Olivier WEBER

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US20180330780A1

公开(公告)日：2018-11-15

申请号：US15978003

申请日：2018-05-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT ,  Olivier WEBER

IPC: G11C13/00 ,  H01L45/00

Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.

公开(公告)号：US20230263082A1

公开(公告)日：2023-08-17

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8265 ,  H10N70/8413 ,  G11C2013/008

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US20190312088A1

公开(公告)日：2019-10-10

申请号：US16375571

申请日：2019-04-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe BOIVIN ,  Jean Jacques FAGOT ,  Emmanuel PETITPREZ ,  Emeline SOUCHIER ,  Olivier WEBER

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US20190140176A1

公开(公告)日：2019-05-09

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.