公开(公告)号：US11765987B2

公开(公告)日：2023-09-19

申请号：US17642706

申请日：2021-01-05

申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

发明人： Xiaomin Cheng ,  Han Li ,  Yuntao Zeng ,  Yunlai Zhu ,  Xiangjun Liu ,  Xiangshui Miao

IPC分类号： H10N70/00 ,  H10N70/20

CPC分类号： H10N70/828 ,  H10N70/066 ,  H10N70/231 ,  H10N70/841 ,  H10N70/8616 ,  H10N70/8828

摘要： A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

公开(公告)号：US11963466B2

公开(公告)日：2024-04-16

申请号：US17330610

申请日：2021-05-26

申请人： Infineon Technologies AG

发明人： Dominik Heiss ,  Christoph Kadow ,  Matthias Markert

IPC分类号： H10N70/20 ,  H10N70/00

CPC分类号： H10N70/253 ,  H10N70/066 ,  H10N70/823 ,  H10N70/8265 ,  H10N70/8613 ,  H10N70/231 ,  H10N70/8616 ,  H10N70/8828

摘要： A switch device including a semiconductor substrate is provided. A trench is formed in the substrate, and a phase change material is provided at least partially in the trench. A heater for heating the phase change material is also provided.

公开(公告)号：US20240099168A1

公开(公告)日：2024-03-21

申请号：US18467653

申请日：2023-09-14

申请人： Commissariat à I'Énergie Atomique et aux Énergies Alternatives

发明人： Gabriele Navarro ,  Guillaume Bourgeois ,  Marie-Claire Cyrille

IPC分类号： H10N70/00 ,  H10B63/10 ,  H10N70/20

CPC分类号： H10N70/8616 ,  H10B63/10 ,  H10N70/011 ,  H10N70/231 ,  H10N70/8413

摘要： A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and first stack comprising a third encapsulation layer coating the side faces of the second layer and a fourth encapsulation layer coating the third layer and being in a material having a lower density than that of the material of the third layer.

公开(公告)号：US11723292B2

公开(公告)日：2023-08-08

申请号：US16910609

申请日：2020-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Yu-Wen Liao ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Sheng-Hung Shih ,  Wen-Chun You

IPC分类号： H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8265 ,  H10B63/30 ,  H10N70/011 ,  H10N70/063 ,  H10N70/066 ,  H10N70/20 ,  H10N70/24 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  H10N70/021 ,  H10N70/023 ,  H10N70/026 ,  H10N70/028 ,  H10N70/041 ,  H10N70/043 ,  H10N70/046 ,  H10N70/061 ,  H10N70/068 ,  H10N70/231 ,  H10N70/235 ,  H10N70/245 ,  H10N70/25 ,  H10N70/253 ,  H10N70/257 ,  H10N70/801 ,  H10N70/821 ,  H10N70/823 ,  H10N70/828 ,  H10N70/8413 ,  H10N70/8416 ,  H10N70/8418 ,  H10N70/8613 ,  H10N70/8616 ,  H10N70/881 ,  H10N70/882 ,  H10N70/883 ,  H10N70/884 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8836 ,  H10N70/8845

摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

公开(公告)号：US20240284809A1

公开(公告)日：2024-08-22

申请号：US18650104

申请日：2024-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chao Lin ,  Yu-Sheng Chen ,  Carlos H. Diaz ,  Da-Ching Chiou

IPC分类号： H10N70/20 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/231 ,  H01L23/5283 ,  H10B63/00 ,  H10N70/063 ,  H10N70/8265 ,  H10N70/841 ,  H10N70/8616

摘要： A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.

公开(公告)号：US20230403955A1

公开(公告)日：2023-12-14

申请号：US18330515

申请日：2023-06-07

申请人： Kioxia Corporation

发明人： Ryouji MASUDA ,  Hiroki TOKUHIRA

IPC分类号： H10N70/00 ,  H10B63/10 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8616 ,  H10B63/10 ,  H10B63/20 ,  H10B63/80 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/063

摘要： A semiconductor memory device includes: a first wiring extending in a first direction; a second wiring extending in a second direction that intersects with the first direction; a resistance change film provided between the first wiring and the second wiring and including at least one element selected from a group consisting of germanium, antimony, and tellurium; an electrode provided between the resistance change film and the first wiring; and a first film selectively provided between the electrode and the first wiring, in which the electrode includes a surface in contact with both of the first wiring and the first film.

公开(公告)号：US11778837B2

公开(公告)日：2023-10-03

申请号：US17846731

申请日：2022-06-22

申请人： Micron Technology, Inc.

发明人： Lei Wei ,  Pengyuan Zheng ,  Kevin Lee Baker ,  Efe Sinan Ege ,  Adam Thomas Barton ,  Rajasekhar Venigalla

IPC分类号： H01L27/24 ,  H01L45/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10B63/84 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8616

摘要： A memory system may include separate amounts or types of resistive material that may be deposited over memory cells and conductive vias using separate resistive layers in the access lines. A first resistive material layer may be deposited over the memory cells prior to performing an array termination etch used to deposit the conductive via. The array termination etch may remove the first resistive material over the portion of the array used to deposit the conductive via. A second resistive material layer may be deposited after the etch has occurred and the conductive via has been formed. The second resistive material layer may be deposited over the conductive via.

公开(公告)号：US20230263082A1

公开(公告)日：2023-08-17

申请号：US18130184

申请日：2023-04-03

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC分类号： H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8265 ,  H10N70/8413 ,  G11C2013/008

摘要： An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC分类号： H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

摘要： An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20240224825A1

公开(公告)日：2024-07-04

申请号：US18409413

申请日：2024-01-10

申请人： Micron Technology, Inc.

发明人： Rajasekhar Venigalla ,  Patrick M. Flynn ,  Josiah Jebaraj Johnley Muthuraj ,  Efe Sinan Ege ,  Kevin Lee Baker ,  Tao Nguyen ,  Davis Weymann

IPC分类号： H10N70/00 ,  G11C13/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8616 ,  G11C13/0004 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  G11C13/004 ,  G11C2013/005 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/8825

摘要： Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.