公开(公告)号：US20190197014A1

公开(公告)日：2019-06-27

申请号：US15850535

申请日：2017-12-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tejinder KUMAR ,  Rathod RONAK KISHORBHAI ,  Apurva SEN ,  Rakesh MALIK

IPC: G06F15/78 ,  G06F17/30

Abstract: Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

公开(公告)号：US20150280728A1

公开(公告)日：2015-10-01

申请号：US14230370

申请日：2014-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Pratap Narayan SINGH ,  Ashish Sharma KUMAR ,  Chandrajit DEBNATH ,  Rakesh MALIK

IPC: H03M1/46 ,  H03M1/12

CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract translation: 异步SAR ADC，以高效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。