公开(公告)号：US20230168291A1

公开(公告)日：2023-06-01

申请号：US17969315

申请日：2022-10-19

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sri Ram GUPTA

IPC: G01R29/26 ,  H03K3/03 ,  H03K3/037

CPC classification number: G01R29/26 ,  H03K3/0315 ,  H03K3/037

Abstract: A measurement is made of jitter present in a jittery clock signal. A digital sinusoid generator circuit clocked by the jittery clock signal generates a pulse density modulation (PDM) signal corresponding to a sinusoid waveform. The PDM signal is converted by a sigma-delta modulator circuit to an oscillating frequency signal with an output of digital values digital values indicative of oscillating frequency signal phase. Responsive to the jittery clock signal, the digital values indicative of oscillating frequency signal phase are sampled. A digital differentiator circuit determines a digital difference between consecutive samples of the digital values indicative of oscillating frequency signal phase. The digital difference is processed by a digital signal processing circuit to generate a frequency spectrum and determine from signal-to-noise ratio a measurement of jitter in the jittery clock signal.

公开(公告)号：US20220321140A1

公开(公告)日：2022-10-06

申请号：US17707113

申请日：2022-03-29

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics International N.V.

Inventor： Nicolas MOENECLAEY ,  Sri Ram GUPTA

IPC: H03M1/46 ,  H03M1/12

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

公开(公告)号：US20220006467A1

公开(公告)日：2022-01-06

申请号：US17342416

申请日：2021-06-08

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ankur BAL ,  Sri Ram GUPTA ,  Rupesh SINGH

IPC: H03M1/10 ,  H03M1/38

Abstract: An integrated circuit includes a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC includes a bit step selector. During testing of the ADC, the bit step selector selects a number of bits to be tested for a next analog test voltage based on digital values that are within an integer delta value of most recent digital value for a most recent analog test voltage.