公开(公告)号：US20240006277A1

公开(公告)日：2024-01-04

申请号：US18369652

申请日：2023-09-18

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/49503 ,  H01L23/4952

Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.

公开(公告)号：US20200235045A1

公开(公告)日：2020-07-23

申请号：US16745043

申请日：2020-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

公开(公告)号：US20190181076A1

公开(公告)日：2019-06-13

申请号：US16213540

申请日：2018-12-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario VITELLO ,  Fabio MARCHISI ,  Alberto ARRIGONI ,  Federico FREGO ,  Federico Giovanni ZIGLIOLI ,  Paolo CREMA

IPC: H01L23/495 ,  H01L21/48 ,  B26F1/38 ,  B23C3/13 ,  C23F1/02

Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.

公开(公告)号：US20170125371A1

公开(公告)日：2017-05-04

申请号：US15175930

申请日：2016-06-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Pierangelo MAGNI ,  Alberto ARRIGONI

IPC: H01L23/00

Abstract: In an embodiment, a semiconductor device includes: a mounting substrate having electrically conductive formations thereon, a semiconductor die coupled with the mounting substrate, the semiconductor die with electrical contact pillars facing towards the mounting substrate, an anisotropic conductive membrane between the semiconductor die and the mounting substrate, the membrane compressed between the electrical contact pillars and the mounting substrate to provide electrical contact between the electrical contact pillars of the semiconductor die and the electrically conductive formations on the mounting substrate.