公开(公告)号：US20220238405A1

公开(公告)日：2022-07-28

申请号：US17573339

申请日：2022-01-11

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni GRAZIOSI ,  Aurora SANNA ,  Riccardo VILLA

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01Q1/22

Abstract: An antenna-in-package semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulation body encapsulates the semiconductor chip. The encapsulation body includes a through cavity extending to the planar substrate. A rectilinear wire antenna is mounted within the through cavity and extends, for instance from the planar substrate, along an axis that is transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The rectilinear wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulated the rectilinear wire antenna.

公开(公告)号：US20220173064A1

公开(公告)日：2022-06-02

申请号：US17537112

申请日：2021-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Cristina SOMMA ,  Aurora SANNA ,  Damian HALICKI

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor die is mounted at a die area of a ball grid array package that includes an array of electrically-conductive ball. A power channel conveys a power supply current to the semiconductor die. The power channel is formed by an electrically-conductive connection plane layers extending in a longitudinal direction between a distal end at a periphery of the package and a proximal end at the die area. A distribution of said electrically-conductive balls is made along the longitudinal direction. The electrically-conductive connection plane layer includes subsequent portions in the longitudinal direction between adjacent electrically-conductive balls of the distribution. Respective electrical resistance values of the subsequent portions monotonously decrease from the distal end to the proximal end. A uniform distribution of power supply current over the length of the power channel is thus facilitated.

公开(公告)号：US20200235045A1

公开(公告)日：2020-07-23

申请号：US16745043

申请日：2020-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

Abstract: A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.

公开(公告)号：US20240145364A1

公开(公告)日：2024-05-02

申请号：US18386069

申请日：2023-11-01

Applicant: STMicroelectronics S.r.l.

Inventor： Aurora SANNA ,  Cristina SOMMA ,  Damian HALICKI

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L23/49816 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5286

Abstract: A BGA package includes an array of electrically conductive balls providing electrical contact for a semiconductor die. A power channel is provided to convey power supply current towards the semiconductor die. The power channel is formed by a stack of electrically conductive planes. The electrically conductive planes are stacked in a stepped arrangement wherein a number of stacked planes in each step of the stack increases in a direction from a distal end to a proximal end of the power channel. Adjacent electrically conductive planes in the stack of the power channel are electrically coupled with electrically conductive vias extending therebetween. Current conduction paths towards the die area thus have resistance values that decrease from the distal end to the proximal end of the power channel.

公开(公告)号：US20240006277A1

公开(公告)日：2024-01-04

申请号：US18369652

申请日：2023-09-18

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto ARRIGONI ,  Giovanni GRAZIOSI ,  Aurora SANNA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49589 ,  H01L21/4825 ,  H01L23/49503 ,  H01L23/4952

Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.