公开(公告)号：US20240096412A1

公开(公告)日：2024-03-21

申请号：US18464093

申请日：2023-09-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino CONTE ,  Agatino Massimo MACCARRONE ,  Francesco TOMAIUOLO ,  Thomas JOUANNEAU ,  Vincenzo RUSSO

IPC: G11C13/00 ,  H03K19/0185 ,  H03K19/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  H03K19/018521 ,  H03K19/20

Abstract: In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.

公开(公告)号：US20230333583A1

公开(公告)日：2023-10-19

申请号：US18295774

申请日：2023-04-04

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Antonino CONTE ,  Marco RUTA ,  Francesco TOMAIUOLO ,  Michelangelo PISASALE ,  Marion Helne GRIMAL

IPC: G05F1/59 ,  G05F1/575

CPC classification number: G05F1/59 ,  G05F1/575

Abstract: A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica. The first and second drivers can be controllably switched between a first mode of operation, during which the current flow path through the driver transistors is conductive or non-conductive based on the voltage-pumped replica of the comparison signal, and a second mode, during which the voltage refresh transistor circuitry is activated to transfer the voltage-pumped replica of the comparison signal, and the current flow path through the driver transistors is non-conductive.

公开(公告)号：US20220334720A1

公开(公告)日：2022-10-20

申请号：US17721933

申请日：2022-04-15

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS S.r.l.

Inventor： Leonardo VALENCIA RISSETTO ,  Francesco TOMAIUOLO ,  Diego DE COSTANTINI

IPC: G06F3/06

Abstract: In response to a request to store new data at a memory location of a bitwise programmable non-volatile memory, data stored at the memory location of the bitwise programmable memory is sensed. The bits of the sensed data are compared with bits of the new data. An indication of a cost difference is determined between a first burst of bitwise programming operations associated with programming bits of the new data which are different from bits of the sensed data, and a second burst of bitwise programming operations associated with programming bits of a complementary inversion of the new data which are different from bits of the sensed data. One of the first burst of bitwise programming operations or the second burst of bitwise programming operations is executed based on the generated indication of the cost difference.