公开(公告)号：US20240096412A1

公开(公告)日：2024-03-21

申请号：US18464093

申请日：2023-09-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino CONTE ,  Agatino Massimo MACCARRONE ,  Francesco TOMAIUOLO ,  Thomas JOUANNEAU ,  Vincenzo RUSSO

IPC: G11C13/00 ,  H03K19/0185 ,  H03K19/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  H03K19/018521 ,  H03K19/20

Abstract: In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.