公开(公告)号：US20040225799A1

公开(公告)日：2004-11-11

申请号：US10434821

申请日：2003-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: H05K007/10 ,  G06F013/00

CPC classification number: G06K19/07

Abstract: An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.

Abstract translation: 用于智能卡的集成电路可以包括收发器和用于与收发器协作以从主机设备接收操作请求的控制器。 控制器可以基于相应的操作请求执行智能卡操作。 此外，控制器还可以与收发器协作以从主机设备接收至少一个提前请求，以指示至少一个操作请求将遵循。 作为示例，备用操作可以包括在至少一个缓冲器中加载数据，其可以基于接收到至少一个操作请求而被发送到主机设备。 其他备用操作可以包括例如当主机设备的通信总线被占用时停止向主机设备的数据传输，并停止执行当前的智能卡操作以允许执行更高优先级的智能卡操作。

公开(公告)号：US20040250191A1

公开(公告)日：2004-12-09

申请号：US10457294

申请日：2003-06-09

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: G01R031/28 ,  G06F011/00

CPC classification number: G06F11/263 ,  G06K7/0013 ,  G06K7/0095 ,  G06K7/10465 ,  G06K19/07

Abstract: A system of the present invention tests the design of a universal serial bus (USB) smartcard device and includes a bus analyzer for running test cases to generate USB bus traffic. A processor is operatively connected to the bus analyzer for receiving and transforming data about USB traffic into a selected data format that is usable across different smartcard development environments.

Abstract translation: 本发明的系统测试通用串行总线（USB）智能卡设备的设计，并且包括用于运行测试用例以生成USB总线业务的总线分析器。 处理器可操作地连接到总线分析器，用于将关于USB流量的数据接收和转换成可在不同智能卡开发环境中使用的所选择的数据格式。

公开(公告)号：US20040249625A1

公开(公告)日：2004-12-09

申请号：US10454178

申请日：2003-06-04

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: G06F009/455

CPC classification number: G06K19/0719 ,  G06F11/261 ,  G06K7/0013 ,  G06K19/07 ,  G06K19/07733

Abstract: An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality of operational modes. The smart card connector may include a plurality of contacts. Moreover, the emulator may further include a plurality of cable assemblies having first ends connected to the emulation circuitry, where each cable assembly is for a respective operational mode. Further, the emulator may also include an interface device connected between second ends of the plurality of cable assemblies and the smart card connector for selectively electrically connecting a selected cable assembly to predetermined ones of the contacts of the smart card connector based upon the at least one operational mode of the smart card adapter.

Abstract translation: 用于多模式智能卡的仿真器可以包括用于在多个操作模式中执行智能卡应用的仿真电路。 仿真器还可以包括要连接到在多个操作模式中的至少一个中可操作的智能卡适配器的智能卡连接器。 智能卡连接器可以包括多个触点。 此外，仿真器还可以包括多个电缆组件，其具有连接到仿真电路的第一端，其中每个电缆组件用于相应的操作模式。 此外，仿真器还可以包括连接在多个电缆组件的第二端和智能卡连接器之间的接口装置，用于基于所述至少一个电连接器选择性地将所选择的电缆组件电连接到智能卡连接器的预定触点 智能卡适配器的操作模式。

公开(公告)号：US20040238644A1

公开(公告)日：2004-12-02

申请号：US10452356

申请日：2003-06-02

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: G06K019/06

CPC classification number: G06K19/06206 ,  G06K19/07

Abstract: An emulator for a smart card device and associated method have at least two virtual components as functional blocks for a smart card device and operative in different clock domains. A functional buffering block is operative for communicating with the functional blocks and buffering between the functional blocks and allowing emulation.

Abstract translation: 用于智能卡设备和相关方法的仿真器具有至少两个虚拟组件作为智能卡设备的功能块并且在不同时钟域中操作。 功能缓冲块用于与功能块通信和功能块之间的缓冲并允许仿真。

公开(公告)号：US20040225918A1

公开(公告)日：2004-11-11

申请号：US10434820

申请日：2003-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Serge Fruhauf ,  Taylor J. Leaming ,  Alain C. Pomet

IPC: H04B001/74

CPC classification number: G06K7/10465 ,  G06K7/0008 ,  G06K7/0095 ,  G06K19/07 ,  G06K19/07733

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.

Abstract translation: 用于智能卡的集成电路可以包括用于与USB主机设备通信的通用串行总线（USB）收发器和连接到USB收发器的微处理器，并且可以在测试模式和用户模式下操作。 当处于测试模式时，微处理器可以经由至少一个USB收发器从USB主机设备接收至少一个测试供应商特定请求（VSR）来执行测试操作。 作为示例，测试操作可以包括对微处理器的控制逻辑进行扫描测试，检测至少一个缓冲器的状态并将状态传送到USB主机设备，将测试数据写入至少一个指定的缓冲器，并将测试数据从 所述至少一个指定的缓冲器到达所述USB主机设备，和/或以降低的功率运行。

公开(公告)号：US20040225888A1

公开(公告)日：2004-11-11

申请号：US10434913

申请日：2003-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Taylor J. Leaming

IPC: H04L009/00

CPC classification number: G07F7/1008 ,  G01R31/31719 ,  G06F21/606 ,  G06F21/77 ,  G06Q20/341 ,  G06Q20/346 ,  G06Q20/3576 ,  G07F7/084

Abstract: An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for communicating with a host device using the default requests and alternate requests. The microprocessor may selectively switch between using the default requests and the alternate requests when communicating with the host device. As such, this provides a nullmoving targetnull which makes it difficult for would-be hackers to determine which requests are used for which smart card operations and, thus, to decipher and interfere with data communications.

Abstract translation: 集成电路（IC）可以包括用于存储一组默认请求的至少一个智能卡存储器和用于每个默认请求的至少一个替代请求。 IC还可以包括连接到至少一个智能卡存储器的微处理器，用于使用默认请求和备用请求与主机设备进行通信。 当与主机设备进行通信时，微处理器可以选择性地切换使用默认请求和备用请求。 因此，这提供了一个“移动目标”，这使得黑客难以确定哪些请求被用于哪个智能卡操作，并因此来破译和干扰数据通信。

公开(公告)号：US20040222305A1

公开(公告)日：2004-11-11

申请号：US10458696

申请日：2003-06-10

Applicant: STMicroelectronics, Inc. ,  State of Incorporation: Delaware

Inventor： Taylor J. Leaming

IPC: G06K019/06

CPC classification number: G01R31/318555 ,  G01R31/3025 ,  G01R31/31719 ,  G06F11/267 ,  G06F11/27 ,  G06K7/0013 ,  G06K7/0095 ,  G06K7/10465 ,  G06K19/07 ,  G06K19/07733

Abstract: An integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation. Further, the integrated circuit may also include a processor for causing the JTAG test controller to initiate the at least one test operation based upon receiving at least one test request from the host device via the transceiver. More particularly, the processor may convert the at least one test request to JTAG data for the JTAG test controller. That is, the integrated circuit advantageously allows communications between the host device and the JTAG controller via a system bus, for example, without the need for a dedicated JTAG test access port (TAP) which is typically required for accessing JTAG controllers.

Abstract translation: 用于智能卡的集成电路可以包括用于与主机设备通信的收发器和用于执行至少一个测试操作的联合测试动作组（JTAG）测试控制器。 此外，集成电路还可以包括处理器，用于使得JTAG测试控制器基于经由收发器从主机设备接收至少一个测试请求来发起至少一个测试操作。 更具体地，处理器可以将至少一个测试请求转换为用于JTAG测试控制器的JTAG数据。 也就是说，集成电路有利地允许例如通过系统总线在主机设备和JTAG控制器之间进行通信，而不需要通常需要访问JTAG控制器的专用JTAG测试访问端口（TAP）。