Abstract:
An integrated circuit for a smart card may include a transceiver for communicating with a host device and a Joint Test Action Group (JTAG) test controller for performing at least one test operation. Further, the integrated circuit may also include a processor for causing the JTAG test controller to initiate the at least one test operation based upon receiving at least one test request from the host device via the transceiver. More particularly, the processor may convert the at least one test request to JTAG data for the JTAG test controller. That is, the integrated circuit advantageously allows communications between the host device and the JTAG controller via a system bus, for example, without the need for a dedicated JTAG test access port (TAP) which is typically required for accessing JTAG controllers.
Abstract:
An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform smart card operations based upon respective operating requests. Moreover, the controller also may cooperate with the transceiver to receive at least one advance request from the host device to indicate that at least one operating request will follow. By way of example, the standby operation may include loading data in at least one buffer, which may be sent to the host device based upon receiving the at least one operating request. Other standby operations may include disabling data transmission to the host device, such as when the communications bus of the host device is preoccupied, and ceasing performing a current smart card operation to allow a higher priority smart card operation to be performed, for example.
Abstract:
A system of the present invention tests the design of a universal serial bus (USB) smartcard device and includes a bus analyzer for running test cases to generate USB bus traffic. A processor is operatively connected to the bus analyzer for receiving and transforming data about USB traffic into a selected data format that is usable across different smartcard development environments.
Abstract:
An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality of operational modes. The smart card connector may include a plurality of contacts. Moreover, the emulator may further include a plurality of cable assemblies having first ends connected to the emulation circuitry, where each cable assembly is for a respective operational mode. Further, the emulator may also include an interface device connected between second ends of the plurality of cable assemblies and the smart card connector for selectively electrically connecting a selected cable assembly to predetermined ones of the contacts of the smart card connector based upon the at least one operational mode of the smart card adapter.
Abstract:
An emulator for a smart card device and associated method have at least two virtual components as functional blocks for a smart card device and operative in different clock domains. A functional buffering block is operative for communicating with the functional blocks and buffering between the functional blocks and allowing emulation.
Abstract:
An integrated circuit for a smart card may include a universal serial bus (USB) transceiver for communicating with a USB host device, and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. When in the test mode, the microprocessor may perform a test operation based upon receiving at least one test vendor specific request (VSR) from the USB host device via the at least one USB transceiver. By way of example, the test operation may include scan testing the microprocessor's control logic, detecting a status of at least one buffer and communicating the status to the USB host device, writing test data to at least one designated buffer and sending the test data from the at least one designated buffer to the USB host device, and/or operating with reduced power.
Abstract:
An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for communicating with a host device using the default requests and alternate requests. The microprocessor may selectively switch between using the default requests and the alternate requests when communicating with the host device. As such, this provides a nullmoving targetnull which makes it difficult for would-be hackers to determine which requests are used for which smart card operations and, thus, to decipher and interfere with data communications.