公开(公告)号：US11754758B2

公开(公告)日：2023-09-12

申请号：US17482237

申请日：2021-09-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Vincent Farys ,  Alain Inard ,  Olivier Noblanc

IPC: G02B5/02 ,  C23C16/34 ,  C23C16/56 ,  C23C18/12

CPC classification number: G02B5/0263 ,  C23C16/345 ,  C23C16/56 ,  C23C18/1208 ,  G02B5/0236 ,  G02B5/0268

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

公开(公告)号：US11150388B2

公开(公告)日：2021-10-19

申请号：US15610150

申请日：2017-05-31

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Vincent Farys ,  Alain Inard ,  Olivier Noblanc

IPC: G02B5/02 ,  C23C16/34 ,  C23C16/56 ,  C23C18/12

Abstract: Methods of manufacture of an optical diffuser. In one embodiment, an optical diffuser is formed by providing a wafer including a silicon slice of which an upper face is covered with a first layer made of a first material itself covered with a second layer made of a second selectively etchable material with respect to the first material. The method further includes forming openings in the second layer extending up to the first layer and filling the openings in the second layer with a third material. The method yet further includes bonding a glass substrate to the wafer on the side of its upper face and removing the silicon slice.

公开(公告)号：US09105699B2

公开(公告)日：2015-08-11

申请号：US14167065

申请日：2014-01-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Vincent Farys

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.

Abstract translation: 本发明涉及一种方法，包括：在集成电路的导电材料层（510）上形成牺牲材料的多条平行线（502,504,506），所述平行线由沟槽分开，至少一个 所述线通过将其分割成由空间（S）分开的第一和第二线路部分（504A，504B）的开口（516）沿着其长度被中断; 在所述线路部分的侧面上的所述沟槽中形成间隔物（522,524,526,528,530），并且在所述线路部分之间填充所述开口的至少一部分底部; 通过蚀刻去除牺牲材料; 以及基于由所述间隔物限定的图案形成所述导电材料的互连线（302,304A，304B，306A，306B，308,310）。