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公开(公告)号:US20240186318A1
公开(公告)日:2024-06-06
申请号:US18526384
申请日:2023-12-01
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Christian RIVERO , Joel METZ , Brice ARRAZAT
IPC: H01L27/06 , H01L29/423 , H01L29/66 , H01L29/94
CPC classification number: H01L27/0629 , H01L29/42336 , H01L29/66181 , H01L29/945
Abstract: An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.
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公开(公告)号:US20220005960A1
公开(公告)日:2022-01-06
申请号:US17366585
申请日:2021-07-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Christian RIVERO , Brice ARRAZAT , Julien DELALLEAU , Joel METZ
IPC: H01L29/94 , H01L29/423 , H01L29/788 , H01L27/11524 , H01L49/02 , H01L21/28 , H01L21/265
Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.
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公开(公告)号:US20230327028A1
公开(公告)日:2023-10-12
申请号:US18210155
申请日:2023-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Christian RIVERO , Brice ARRAZAT , Julien DELALLEAU , Joel METZ
IPC: H01L29/94 , H01L21/28 , H01L21/265 , H01L29/423 , H01L29/788 , H10B41/35
CPC classification number: H01L29/945 , H01L29/40114 , H01L21/2652 , H01L28/91 , H01L29/4236 , H01L29/788 , H10B41/35
Abstract: A semiconductor substrate includes excavations which form trenches sunk. A capacitive element includes: a first dielectric envelope conforming to sides and bottoms of the trenches; a first semiconductor layer conforming to a surface of the first dielectric envelope in the trenches; a second dielectric envelope conforming to a surface of the first semiconductor layer in the trenches; and a second semiconductor layer conforming to a surface of the second dielectric envelope in the trenches.
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