公开(公告)号：US20240347481A1

公开(公告)日：2024-10-17

申请号：US18753409

申请日：2024-06-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20230163083A1

公开(公告)日：2023-05-25

申请号：US18095136

申请日：2023-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L23/528

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/4916 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L23/528

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US20190172786A1

公开(公告)日：2019-06-06

申请号：US16260394

申请日：2019-01-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Jean-Philippe ESCALES

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/31 ,  H01L21/311 ,  H01L23/532

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

公开(公告)号：US20240186318A1

公开(公告)日：2024-06-06

申请号：US18526384

申请日：2023-12-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Joel METZ ,  Brice ARRAZAT

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L29/42336 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.

公开(公告)号：US20230223448A1

公开(公告)日：2023-07-13

申请号：US18094023

申请日：2023-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Christian RIVERO ,  Franck JULIEN

IPC: H01L29/40 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/401 ,  H01L29/456 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53266 ,  H01L23/5226

Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.

公开(公告)号：US20190027566A1

公开(公告)日：2019-01-24

申请号：US16036240

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/7881

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190027439A1

公开(公告)日：2019-01-24

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/535 ,  H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US20200176577A1

公开(公告)日：2020-06-04

申请号：US16783401

申请日：2020-02-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11524

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

公开(公告)号：US20190165105A1

公开(公告)日：2019-05-30

申请号：US16241762

申请日：2019-01-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L27/112 ,  H01L29/78 ,  H01L21/763 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20190027447A1

公开(公告)日：2019-01-24

申请号：US16036639

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/00 ,  H01L23/528 ,  H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.