公开(公告)号：US10103721B2

公开(公告)日：2018-10-16

申请号：US15361594

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan

IPC: H03K17/00 ,  H03K5/159 ,  H03K19/003 ,  G06F7/58 ,  H03K3/84 ,  H03K19/173

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US20170324405A1

公开(公告)日：2017-11-09

申请号：US15361594

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan

IPC: H03K17/00 ,  H03K19/003 ,  H03K5/159

CPC classification number: H03K17/005 ,  G06F7/58 ,  H03K3/84 ,  H03K5/159 ,  H03K19/003 ,  H03K19/1737

Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

公开(公告)号：US10075166B2

公开(公告)日：2018-09-11

申请号：US15361708

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan ,  Jean Nicolai

IPC: H03K19/003 ,  H03K5/14 ,  H03K19/20 ,  H03L3/00

CPC classification number: H03K19/003 ,  H03K3/84 ,  H03K5/14 ,  H03K19/20 ,  H03L3/00

Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

公开(公告)号：US20170324409A1

公开(公告)日：2017-11-09

申请号：US15361708

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Albert Martinez ,  Michel Agoyan ,  Jean Nicolai

IPC: H03K19/003 ,  H03K5/14 ,  H03K19/20 ,  H03L3/00

CPC classification number: H03K19/003 ,  H03K3/84 ,  H03K5/14 ,  H03K19/20 ,  H03L3/00

Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.