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公开(公告)号:US20220416053A1
公开(公告)日:2022-12-29
申请号:US17899071
申请日:2022-08-30
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor: Samuel MENARD
IPC: H01L29/47 , H01L29/73 , H01L29/747 , H01L29/74 , H01L29/732 , H01L29/417
Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.
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公开(公告)号:US20250169151A1
公开(公告)日:2025-05-22
申请号:US19029853
申请日:2025-01-17
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor: Samuel MENARD
Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.
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公开(公告)号:US20200258818A1
公开(公告)日:2020-08-13
申请号:US16785956
申请日:2020-02-10
Applicant: STMicroelectronics (Tours) SAS
Inventor: Samuel MENARD , Laurent BARREAU
IPC: H01L23/492 , H01L29/747 , H01L23/00 , H01L23/14
Abstract: A vertical power component includes a semiconductor substrate, a first electrode in contact with a lower surface of the substrate, and a second electrode in contact with an upper surface of the substrate. The vertical component is mounted to a metal connection plate via a metal spacer. The metal spacer includes a lower surface soldered to the metal connection plate and an upper surface soldered to the first electrode of the vertical power component. The metal spacer is made of a same metal as the metal connection plate. A surface are of the metal spacer mounted to the first electrode is smaller than a surface area of the first electrode.
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公开(公告)号:US20190214476A1
公开(公告)日:2019-07-11
申请号:US16230137
申请日:2018-12-21
Applicant: STMICROELECTRONICS (TOURS) SAS
Inventor: Samuel MENARD
IPC: H01L29/47 , H01L29/73 , H01L29/732 , H01L29/74 , H01L29/747
CPC classification number: H01L29/47 , H01L29/456 , H01L29/73 , H01L29/7308 , H01L29/732 , H01L29/74 , H01L29/747
Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.
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公开(公告)号:US20190043972A1
公开(公告)日:2019-02-07
申请号:US16052378
申请日:2018-08-01
Applicant: STMicroelectronics (Tours) SAS
Inventor: Samuel MENARD
IPC: H01L29/747 , H01L29/66
CPC classification number: H01L29/747 , H01L29/0619 , H01L29/0839 , H01L29/42308 , H01L29/66386 , H01L29/7404
Abstract: A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.
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