公开(公告)号：US20220137128A1

公开(公告)日：2022-05-05

申请号：US17083876

申请日：2020-10-29

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH ,  STMicroelectronics S.r.l.

Inventor： Avneep Kumar GOYAL ,  Deepak BARANWAL ,  Thomas SZURMANT ,  Nicolas Bernard GROSSIER

IPC: G01R31/317 ,  G01R31/3185

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

公开(公告)号：US20240296899A1

公开(公告)日：2024-09-05

申请号：US18661914

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/10 ,  G11C7/22 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36 ,  H03K19/20

CPC classification number: G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

公开(公告)号：US20240241811A1

公开(公告)日：2024-07-18

申请号：US18155204

申请日：2023-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar GOYAL ,  Amritanshu ANAND ,  Satinder Singh MALHI

IPC: G06F11/36 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/3656 ,  G06F11/0772 ,  G06F11/1441

Abstract: In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.

公开(公告)号：US20240243945A1

公开(公告)日：2024-07-18

申请号：US18155094

申请日：2023-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Avneep Kumar GOYAL ,  Nicolas GUION ,  Sumit Kumar SINGHAL ,  Jagtar SINGH ,  Dhulipalla Phaneendra KUMAR

IPC: H04L12/40

CPC classification number: H04L12/40143 ,  H04L2012/40215

Abstract: Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.

公开(公告)号：US20230042541A1

公开(公告)日：2023-02-09

申请号：US17443556

申请日：2021-07-27

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan SRINIVASAN ,  Balwinder Singh SONI ,  Avneep Kumar GOYAL

IPC: G11C29/38 ,  G11C7/22 ,  G11C7/10 ,  G11C29/36 ,  G11C29/14

Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.