公开(公告)号：US20240363187A1

公开(公告)日：2024-10-31

申请号：US18635569

申请日：2024-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Christophe LECOCQ ,  Yagnesh Dineshbhai VADERIYA ,  Anuj DHILLON ,  Cedric ESCALLIER ,  Harsh RAWAT ,  Kedar Janardan DHORI

IPC: G11C29/46 ,  G11C29/02 ,  G11C29/32

CPC classification number: G11C29/46 ,  G11C29/022 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.