公开(公告)号：US20150341159A1

公开(公告)日：2015-11-26

申请号：US14817996

申请日：2015-08-04

Applicant: STMicroelectronics N.V.

Inventor： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

Abstract: An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract translation: 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

公开(公告)号：US09130700B2

公开(公告)日：2015-09-08

申请号：US14295233

申请日：2014-06-03

Applicant: STMicroelectronics, N.V.

Inventor： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC: H03L7/16 ,  H04B1/06 ,  H04L7/00 ,  H03H17/06 ,  H04L7/02

CPC classification number: H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

Abstract: Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract translation: 通过在信号路径中添加弹性存储元件来改进插值器和抽取器装置和方法。 在一个示例性实施例中，弹性元件包括有利地允许采样时钟的短期变化被吸收的FIFO，并且还提供用于控制基于Δ-Σ调制的模N计数器的采样时钟发生器的反馈机制。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

公开(公告)号：US20140286467A1

公开(公告)日：2014-09-25

申请号：US14295233

申请日：2014-06-03

Applicant: STMicroelectronics, N.V.

Inventor： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

Abstract: Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract translation: 通过在信号路径中添加弹性存储元件来改善插值器和抽取器装置和方法。 在一个示例性实施例中，弹性元件包括有利地允许采样时钟的短期变化被吸收的FIFO，并且还提供用于控制基于Δ-Σ调制的模N计数器的采样时钟发生器的反馈机制。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。

公开(公告)号：US09325488B2

公开(公告)日：2016-04-26

申请号：US14817996

申请日：2015-08-04

Applicant: STMicroelectronics N.V.

Inventor： Steven R. Norsworthy ,  Jason Rupert Redgrave

IPC: H04L7/00 ,  H03H17/06 ,  H04L7/02

CPC classification number: H04L7/0008 ,  H03H17/0614 ,  H03H17/0628 ,  H03H2218/04 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/02

Abstract: An interpolator or decimator includes an elastic storage element in the signal path between first and second clock domains. The elastic element may, for example, be a FIFO which advantageously allows short term variation in sample clocks to be absorbed. A feedback mechanism controls a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract translation: 内插器或抽取器包括在第一和第二时钟域之间的信号路径中的弹性存储元件。 弹性元件可以例如是有利地允许采样时钟的短期变化被吸收的FIFO。 反馈机制控制基于Δ-Σ调制的模N计数器的采样时钟发生器。 与Δ-Σ调制器和计数器结合的弹性元件产生噪声形式的频率锁定环，而没有额外的组件，导致了非常简化的内插器和抽取器。