公开(公告)号：US09019140B2

公开(公告)日：2015-04-28

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。

公开(公告)号：US08928360B2

公开(公告)日：2015-01-06

申请号：US13854395

申请日：2013-04-01

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Wadeo Ou

IPC: H03K3/00 ,  H03G3/00 ,  H03G3/30

CPC classification number: H03G3/004 ,  H03G3/002 ,  H03G3/3089

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。

公开(公告)号：US20140015699A1

公开(公告)日：2014-01-16

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。