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    Tuner of the type having zero intermediate frequency and corresponding control process
    1.
    发明申请
    Tuner of the type having zero intermediate frequency and corresponding control process 有权
    调谐器具有零中频和相应的控制过程

    公开(公告)号：US20020003586A1

    公开(公告)日：2002-01-10

    申请号：US09827306

    申请日：2001-04-05

    Applicant: STMicroelectronics S.A.

    Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Frederic Paillardet

    IPC: H04N007/20 ,  H04N005/50

    CPC classification number: H03G3/3068 ,  H03G3/3089

    Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/ amplifier stage being fixed.

    Abstract translation: 调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。 模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。 在初始化阶段计算由调谐器接收的整个信号的总平均功率。 该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。 调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。 在正常工作阶段，选择所接收信号的通道之一，第一衰减器/放大器级的增益是固定的。

    Reduced-size integrated phase-locked loop
    2.
    发明申请
    Reduced-size integrated phase-locked loop 有权
    减小尺寸的集成锁相环

    公开(公告)号：US20040212410A1

    公开(公告)日：2004-10-28

    申请号：US10776931

    申请日：2004-02-11

    Applicant: STMicroelectronics S.A.

    Inventor： Mostafa Ghazali ,  Pierre-Olivier Jouffre

    IPC: H03L007/06

    CPC classification number: H03L7/18 ,  H03L7/0891 ,  H03L7/0996

    Abstract: A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.

    Abstract translation: 一种锁相环，包括比较器，其产生取决于参考信号和反馈信号之间的相移的控制电压，由控制电压控制的振荡器，产生相同周期的多个相移信号，其中之一形成 输出信号的多路复用器，能够将任何相移信号提供给分频器的输入，分频器的输出形成反馈信号，以及控制多路复用器的装置，以连续地提供相位的分数 转换信号，使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。

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