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公开(公告)号：US11996158B2
公开(公告)日：2024-05-28
申请号：US18349565
申请日：2023-07-10
Applicant: STMicroelectronics S.r.I.
Inventor： Giampiero Borgonovo , Lorenzo Re Fiorentin
CPC classification number: G11C29/42 , G11C29/12015 , G11C29/18 , G11C29/4401
Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
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公开(公告)号：US20240095057A1
公开(公告)日：2024-03-21
申请号：US18457229
申请日：2023-08-28
Applicant: STMicroelectronics S.r.I.
Inventor： Giampiero Borgonovo , Lorenzo Re Fiorentin
IPC: G06F9/455
CPC classification number: G06F9/45558 , G06F2009/45583 , G06F2009/45595
Abstract: A system, for use in providing media access control (MAC)/router/switch/gateway features in an on-board communication network in a vehicle, includes MAC controllers configured to provide a MAC port layer controlling exchange of information over a data link, virtual machine (VM) bridge blocks configured to provide a MAC frame layer interfacing with System-on-Chip VMs, a software (SW) Ethernet port configured to receive from a host programming/configuration information for the system, a local memory controller configured to facilitate the MAC controllers, the VM bridge blocks and the SW Ethernet port in cooperating with a local memory (LMEM), and queue handlers configured to provide queue management for the MAC controllers, the VM bridge blocks and the SW Ethernet port, during cooperation with the LMEM via the local memory controller.
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公开(公告)号：US20230360716A1
公开(公告)日：2023-11-09
申请号：US18349565
申请日：2023-07-10
Applicant: STMicroelectronics S.r.I.
Inventor： Giampiero Borgonovo , Lorenzo Re Fiorentin
CPC classification number: G11C29/42 , G11C29/12015 , G11C29/18 , G11C29/4401
Abstract: A device includes a set of processing circuits arranged in subsets, a set of data memory banks coupled to a memory controller, a control unit, and an interconnect network. The processing circuits are configurable to read first input data from the data memory banks via the interconnect network and the memory controller, process the first input data to produce output data, and write the output data into the data memory banks via the interconnect network and the memory controller. The hardware accelerator device includes a set of configurable lock-step control units which interface the processing circuits to the interconnect network. Each configurable lock-step control unit is coupled to a subset of processing circuits and is selectively activatable to operate in a first operation mode, or in a second operation mode.
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公开(公告)号：US09558052B2
公开(公告)日：2017-01-31
申请号：US14218482
申请日：2014-03-18
Inventor： Om Ranjan , Giampiero Borgonovo , Deepak Baranwal
CPC classification number: G06F11/0736 , G05B19/0428 , G05B23/0254 , G05B2219/2637 , G06F11/2205 , G06F11/3013
Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.
Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。
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