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公开(公告)号：US11342885B2
公开(公告)日：2022-05-24
申请号：US16698060
申请日：2019-11-27
Applicant: STMicroelectronics S.r.l.
Inventor： Alessia Maria Elgani , Francesco Renzini , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Canegallo , Giulio Ricotti
Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
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公开(公告)号：US20230318532A1
公开(公告)日：2023-10-05
申请号：US18191485
申请日：2023-03-28
Inventor： Alessia Maria Elgani , Matteo D'Addato , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Antonio Canegallo , Giulio Ricotti
CPC classification number: H03F1/0222 , H03F1/32 , H03F2200/102
Abstract: In accordance with an embodiment, an envelope detector includes a first transistor having a first current conduction terminal coupled to a first connection node; a second current conduction terminal coupled to an intermediate node; and a control terminal coupled the signal input node and to a biasing node; a second transistor having a first current conduction terminal coupled to the intermediate node; a second current conduction terminal coupled to a second connection node; and a control terminal coupled to the biasing node; and a first temperature compensating transistor that is diode-connected and coupled between a compensation output node and the biasing node. The second connection node is coupled to the compensation output node and the first connection node is coupled to a detector output.
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公开(公告)号：US20200177133A1
公开(公告)日：2020-06-04
申请号：US16698060
申请日：2019-11-27
Applicant: STMicroelectronics S.r.l.
Inventor： Alessia Maria Elgani , Francesco Renzini , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Canegallo , Giulio Ricotti
Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
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公开(公告)号：US20240056060A1
公开(公告)日：2024-02-15
申请号：US18359465
申请日：2023-07-26
Inventor： Matteo D'Addato , Alessia Maria Elgani , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Antonio Canegallo , Giulio Ricotti
IPC: H03K3/0233 , H04L25/06 , H04L27/06 , H03L7/099
CPC classification number: H03K3/0233 , H04L25/06 , H04L27/06 , H03L7/0995
Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.
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