公开(公告)号：US11342885B2

公开(公告)日：2022-05-24

申请号：US16698060

申请日：2019-11-27

Applicant: STMicroelectronics S.r.l.

Inventor： Alessia Maria Elgani ,  Francesco Renzini ,  Luca Perilli ,  Eleonora Franchi Scarselli ,  Antonio Gnudi ,  Roberto Canegallo ,  Giulio Ricotti

IPC: H03F1/02 ,  H03D1/10 ,  H03D1/18 ,  H03F3/193

Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.

公开(公告)号：US09219481B2

公开(公告)日：2015-12-22

申请号：US14615915

申请日：2015-02-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Mauro Scandiuzzo ,  Salvatore Valerio Cani ,  Claudio Mucci ,  Roberto Canegallo ,  Pier Luigi Rolandi

IPC: H03L5/00 ,  H03K19/0185 ,  H03K17/16

CPC classification number: H03K19/018507 ,  H03K17/16 ,  H03K19/018521 ,  Y10T29/49155

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

公开(公告)号：US08981830B2

公开(公告)日：2015-03-17

申请号：US13753390

申请日：2013-01-29

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro Scandiuzzo ,  Salvatore Valerio Cani ,  Claudio Mucci ,  Roberto Canegallo ,  Pier Luigi Rolandi

IPC: H03L5/00 ,  H03K17/16 ,  H03K19/0185

CPC classification number: H03K19/018507 ,  H03K17/16 ,  H03K19/018521 ,  Y10T29/49155

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

Abstract translation: 一种异步电平移位器电子电路，包括：发射机，其可耦合到第一电压并产生通信信号; 接收器，其可以耦合到第二电压; 以及电容耦合级，其接收通信信号并将相应的滤波信号提供给接收器。 接收机包括：阈值装置，其具有输入端子和输出端子，并且在第一值和第二值之间切换输出端子上的电量，作为通过存在的第一中间信号的阈值的相应转换的函数 在所述输入端子上产生第二中间信号; 以及偏置电路，其产生具有直流的第一中间信号。 分量，其是第二中间信号的函数，并且叠加在其上，其是作为滤波信号的函数的可变分量。

公开(公告)号：US20220068380A1

公开(公告)日：2022-03-03

申请号：US17462250

申请日：2021-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Roberto Canegallo

IPC: G11C13/00

Abstract: An embodiment memory device comprises a plurality of memory cells, each exhibiting a transconductance depending on a value of a stored bit, a plurality of bit lines associated with respective groups of memory cells, each bit line configured to flow a respective electric current indicative of the bit stored in a selected memory cell of the respective group of memory cells, and a computing circuit providing an output electric quantity indicative of a linear combination of a plurality of input electric quantities. The computing circuit comprises a biasing stage configured to bias each bit line with a respective input electric quantity, the electric current flowing through each bit line based on a product of the respective input electric quantity and the transconductance of the selected memory cell, and a combining stage for combining the electric currents flowing through the plurality of bit lines thereby obtaining the output electric quantity.

公开(公告)号：US20200025843A1

公开(公告)日：2020-01-23

申请号：US16514469

申请日：2019-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Crescentini ,  Michele Biondi ,  Marco Tartagni ,  Aldo Romani ,  Roberto Canegallo

IPC: G01R33/07

Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.

公开(公告)号：US20200177133A1

公开(公告)日：2020-06-04

申请号：US16698060

申请日：2019-11-27

Applicant: STMicroelectronics S.r.l.

Inventor： Alessia Maria Elgani ,  Francesco Renzini ,  Luca Perilli ,  Eleonora Franchi Scarselli ,  Antonio Gnudi ,  Roberto Canegallo ,  Giulio Ricotti

IPC: H03F1/02 ,  H03D1/10 ,  H03D1/18 ,  H03F3/193

Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.

公开(公告)号：US20150381177A1

公开(公告)日：2015-12-31

申请号：US14744288

申请日：2015-06-19

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Canegallo ,  Luca Perilli ,  Luca Perugini ,  Salvatore Valerio Cani ,  Eleonora Franchi

IPC: H03K19/0175 ,  H03K19/0948

CPC classification number: H03K19/0175 ,  G01R31/2886 ,  G01R31/44 ,  H03K19/0185 ,  H03K19/0948

Abstract: A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition.

Abstract translation: 用于集成电路的通信单元包括被配置为提供输入信号（例如，电容信号或欧姆信号）的物理接口。 接收器电路用于接收电容信号并产生第一中间信号。 缓冲电路用于接收欧姆信号并产生第二中间信号。 输出级包括被配置为接收第一和第二中间信号的选择器装置（例如，多路复用器），并且基于操作条件选择性地仅将这些信号中的一个传送到集成电路。 输入信号还可以是感应信号，其中输出级还用于基于操作条件选择性地传递该信号。

公开(公告)号：US09432020B2

公开(公告)日：2016-08-30

申请号：US14744288

申请日：2015-06-19

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Canegallo ,  Luca Perilli ,  Luca Perugini ,  Salvatore Valerio Cani ,  Eleonora Franchi

IPC: H03K19/173 ,  H03K19/0175 ,  H03K19/0948 ,  G01R31/28 ,  H03K19/0185

CPC classification number: H03K19/0175 ,  G01R31/2886 ,  G01R31/44 ,  H03K19/0185 ,  H03K19/0948

Abstract: A communication cell for an integrated circuit includes a physical interface configured to supply an input signal (for example, a capacitive signal or an ohmic signal). A receiver circuit operates to receive the capacitive signal and generate a first intermediate signal. A buffer circuit operates to receive the ohmic signal and generate a second intermediate signal. An output stage including a selector device (for example, a multiplexer) configured to receive the first and second intermediate signals and selectively pass only one of those signals to the integrated circuit based on operating condition. The input signal may further be an inductive signal, with the output stage further functioning to selectively pass that signal based on operating condition.

Abstract translation: 用于集成电路的通信单元包括被配置为提供输入信号（例如，电容信号或欧姆信号）的物理接口。 接收器电路用于接收电容信号并产生第一中间信号。 缓冲电路用于接收欧姆信号并产生第二中间信号。 输出级包括被配置为接收第一和第二中间信号的选择器装置（例如，多路复用器），并且基于操作条件选择性地仅将这些信号中的一个传送到集成电路。 输入信号还可以是感应信号，其中输出级还用于基于操作条件选择性地传递该信号。

公开(公告)号：US11119160B2

公开(公告)日：2021-09-14

申请号：US16514469

申请日：2019-07-17

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Crescentini ,  Michele Biondi ,  Marco Tartagni ,  Aldo Romani ,  Roberto Canegallo

IPC: G01R33/06 ,  G01R33/07

Abstract: A planar Hall sensing element includes a first pair of sensing electrodes mutually opposed in a first direction across the sensing element and a second pair of sensing electrodes mutually opposed in a second direction across the sensing element, with the second direction orthogonal to the first direction. A first pair of bias electrodes is mutually opposed in a third direction and a second pair mutually opposed in a fourth direction across the sensing element, the fourth direction orthogonal to the third direction. The third and fourth directions are rotated 45° with respect to the first and second directions so each sensing electrode is arranged between a bias electrode of the first pair and second pair. A DC bias current is supplied between the first and second pairs of bias electrodes. First and second Hall voltages are sensed at the first and second pairs of sensing electrodes.

公开(公告)号：US10571531B2

公开(公告)日：2020-02-25

申请号：US15918809

申请日：2018-03-12

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Crescentini ,  Marco Tartagni ,  Aldo Romani ,  Roberto Canegallo ,  Marco Marchesi ,  Domenico Cristaudo

IPC: G01R33/06 ,  G01R33/07 ,  G01R33/038 ,  G01R33/028 ,  G01R33/02 ,  G01R33/00 ,  B64G1/36 ,  G01R15/20 ,  G01R33/12 ,  G01N27/90 ,  G11C19/08 ,  H01F7/02

Abstract: A Hall sensor may include a Hall sensing element configured to produce a Hall voltage indicative of a magnetic field when traversed by an electric current, and a first pair of bias electrodes mutually opposed in a first direction across the Hall sensing element. The Hall sensor may include a second pair of bias electrodes mutually opposed in a second direction across the Hall sensing element. The Hall sensor may include a first pair of sensing electrodes mutually opposed in a third direction across the Hall sensing element, and a second pair of sensing electrodes mutually opposed in a fourth direction across the Hall sensing element. The fourth direction may be orthogonal to the third direction, each sensing electrode being between a bias electrode of the first pair and a bias electrode of the second pair.