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公开(公告)号：US20240056060A1
公开(公告)日：2024-02-15
申请号：US18359465
申请日：2023-07-26
Inventor： Matteo D'Addato , Alessia Maria Elgani , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Antonio Canegallo , Giulio Ricotti
IPC: H03K3/0233 , H04L25/06 , H04L27/06 , H03L7/099
CPC classification number: H03K3/0233 , H04L25/06 , H04L27/06 , H03L7/0995
Abstract: A circuit includes a clock input node, a first signal input node configured to receive a first modulated signal switching between a first DC voltage and a second DC voltage, a bias circuit, a first output node, a first capacitor, a second capacitor, and switching circuitry coupled to the first capacitor and the second capacitor. Control circuitry is configured to initially set the switching circuitry in a first configuration in response to the first modulated signal having the second DC voltage, thereby charging the first capacitor to the second DC voltage and charging the second capacitor to the first DC voltage, and subsequently set the switching circuitry in a second configuration in response to an edge detected in the clock signal, thereby producing the first threshold voltage at the first output node after charge redistribution taking place between the first and second capacitors.
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公开(公告)号：US20200177133A1
公开(公告)日：2020-06-04
申请号：US16698060
申请日：2019-11-27
Applicant: STMicroelectronics S.r.l.
Inventor： Alessia Maria Elgani , Francesco Renzini , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Canegallo , Giulio Ricotti
Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
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Patent Agency Ranking
公开(公告)号：US11942144B2
公开(公告)日：2024-03-26
申请号：US17582675
申请日：2022-01-24
Inventor： Marco Pasotti , Marcella Carissimi , Antonio Gnudi , Eleonora Franchi Scarselli , Alessio Antolini , Andrea Lico
IPC: G11C11/4096 , G06F7/544 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4094
CPC classification number: G11C11/4096 , G06F7/5443 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4094
Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.
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公开(公告)号：US11342885B2
公开(公告)日：2022-05-24
申请号：US16698060
申请日：2019-11-27
Applicant: STMicroelectronics S.r.l.
Inventor： Alessia Maria Elgani , Francesco Renzini , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Canegallo , Giulio Ricotti
Abstract: In one example, a circuit includes a first node to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal. An output node is configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal. The rising and falling edges are indicative of rising and falling edges of the digital signal. A first current path is disposed between a power supply node and the first node. The first current path includes a first transistor coupled between the first node and a first bias source. The first bias source is coupled between the first transistor and the power supply node. The output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source. A control terminal of the first transistor is coupled to the output node via a feedback network.
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公开(公告)号：US12211582B2
公开(公告)日：2025-01-28
申请号：US17718755
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.
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公开(公告)号：US11894052B2
公开(公告)日：2024-02-06
申请号：US17718908
申请日：2022-04-12
Inventor： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico , Paolo Romele
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
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公开(公告)号：US20230318532A1
公开(公告)日：2023-10-05
申请号：US18191485
申请日：2023-03-28
Inventor： Alessia Maria Elgani , Matteo D'Addato , Luca Perilli , Eleonora Franchi Scarselli , Antonio Gnudi , Roberto Antonio Canegallo , Giulio Ricotti
CPC classification number: H03F1/0222 , H03F1/32 , H03F2200/102
Abstract: In accordance with an embodiment, an envelope detector includes a first transistor having a first current conduction terminal coupled to a first connection node; a second current conduction terminal coupled to an intermediate node; and a control terminal coupled the signal input node and to a biasing node; a second transistor having a first current conduction terminal coupled to the intermediate node; a second current conduction terminal coupled to a second connection node; and a control terminal coupled to the biasing node; and a first temperature compensating transistor that is diode-connected and coupled between a compensation output node and the biasing node. The second connection node is coupled to the compensation output node and the first connection node is coupled to a detector output.
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