公开(公告)号：US20040183158A1

公开(公告)日：2004-09-23

申请号：US10756203

申请日：2004-01-12

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Patti

IPC: H01L029/00

CPC classification number: H01L28/20 ,  H01L27/0658 ,  H01L29/8605

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material. By this means, the portion of the second layer surrounded by the trench defines a first high-voltage resistor having a vertical structure and current flow, whereas the portion of the first layer arranged below the trench defines a second high-voltage resistor arranged in series with the first high-voltage resistor, and also having a vertical structure and current flow.

Abstract translation: 该制造方法包括以下步骤：从半导体材料衬底外延生长第一层，在第一层中形成彼此间隔开并具有与第一层相反类型的导电性的第一和第二掩埋区; 在第一层上外延生长具有与第一层相同类型的导电性的第二层半导体材料; 在所述第二层中形成深度超过所述掩埋区域的沟槽，布置在所述掩埋区域之间，并且在平面图中具有框架形状; 形成覆盖沟槽的侧壁和底壁的氧化物层; 并用隔离材料填充沟槽的剩余部分。 通过这种方式，由沟槽包围的第二层的部分限定了具有垂直结构和电流的第一高压电阻器，而布置在沟槽下方的第一层的部分限定了串联布置的第二高压电阻器 具有第一高压电阻，并具有垂直结构和电流。

公开(公告)号：US20040016960A1

公开(公告)日：2004-01-29

申请号：US10439277

申请日：2003-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Natale Aiello ,  Davide Patti

IPC: H01L029/76 ,  H01L021/332

CPC classification number: H01L27/0676 ,  H01L29/94

Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

Abstract translation: 用于感测集成电路功率器件中的衬底电压的电容器可以通过隔离通常覆盖通常用于电场均衡的重掺杂周边区域的金属层的部分或部分来实现。 结合，如在通常在沉积金属层之前所做的那样，氧化硅隔离介电层的一个或多个部分不从半导体衬底的表面去除。 未被除去的隔离氧化硅部分成为电容器的电介质层。 此外，电容器的一个板由电连接到衬底（例如漏极或集电极区域）的重掺杂周边区域形成。 另一个板由从直接在重掺杂的周边区域上限定的剩余金属层分离的金属段形成。

公开(公告)号：US20040178474A1

公开(公告)日：2004-09-16

申请号：US10735286

申请日：2003-12-12

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Patti

IPC: H01L029/00

CPC classification number: H01L29/735 ,  H01L29/0692 ,  H01L29/0808

Abstract: A lateral-current-flow integrated transistor, formed in an epitaxial layer defining a base well with a first conductivity type, which accommodates emitter and collector regions of a second conductivity type. The collector region is formed by an internal conductive region and by an external conductive region, and the emitter region is formed by an intermediate conductive region. The external conductive region has an annular shape and surrounds the intermediate conductive region, which also has an annular shape and surrounds the internal conductive region.

Abstract translation: 横向电流集成晶体管，形成在限定具有第一导电类型的基极阱的外延层中，其容纳第二导电类型的发射极和集电极区域。 集电极区域由内部导电区域和外部导电区域形成，发射极区域由中间导电区域形成。 外部导电区域具有环形形状并且包围中间导电区域，该中间导电区域也具有环形并且围绕内部导电区域。

公开(公告)号：US20020185677A1

公开(公告)日：2002-12-12

申请号：US10202076

申请日：2002-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Patti ,  Francesco Priolo ,  Vittorio Privitera ,  Giorgia Franzo

IPC: H01L021/8238

CPC classification number: H01L29/0804 ,  H01L21/8234

Abstract: An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

Abstract translation: 电子功率器件集成在具有第一导电类型的半导体衬底上，在其上生长相同导电类型的外延层。 功率器件包括功率级和控制级，后者封装在具有第二导电类型的隔离区中。 功率级包括具有第二导电类型的第一掩埋区域和与第一掩埋区域部分重叠并且具有第一导电类型的第二掩埋区域。 控制级包括具有第二导电类型的第三掩埋区域和与第三掩埋区域重叠并且具有第一导电类型的第四掩埋区域。 所述第一，第二，第三和第四掩埋区域以足以允许功率级和控制级整体形成在外延层中的深度形成在外延层中。

公开(公告)号：US20020017657A1

公开(公告)日：2002-02-14

申请号：US09811159

申请日：2001-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Coffa ,  Davide Patti

IPC: H01L031/072

CPC classification number: H01L21/28273 ,  Y10S438/962

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract translation: 公开了一种在氧化物层中形成硅纳米晶体薄层的工艺。 该方法包括在半导体衬底上将衬底的第一部分热氧化成氧化物层，在氧化物层内形成硅离子，以及热处理硅离子以成为硅纳米晶体的薄层。 在本发明的方法中，硅离子的形成是通过以0.1keV至7keV，优选1至5keV之间的离子化能量将硅离子离子注入氧化物中。 这允许硅原子在比其他可能的温度更低的温度下聚结。 另外，可以通过在多于一个能级执行多于一次的注入来形成多于一层的纳米晶体。 本发明的实施例可用于形成具有非常小尺寸的非常高质量的非易失性存储器件。