公开(公告)号：US20030219119A1

公开(公告)日：2003-11-27

申请号：US10319378

申请日：2002-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ljupco Kocarev ,  Toni Stojanovski ,  Gianguido Rizzotto ,  Francesco Italia ,  Domenico Porto

IPC: H04L009/00

CPC classification number: H04L9/0861 ,  G06F7/588

Abstract: A method for generating a random number sequence whose randomness properties are determined a priori, includes defining a parametric map, calculating, in function of parameters of the map, the entropy and the Lyapunov exponent of random number sequences obtainable using the parametric map, and identifying at least a set of values of parameters for which the entropy and the Lyapunov exponent are positive numbers the map has no attracting point. The method further includes assigning a pre-established value as a first feedback value and cyclically carrying out the following steps for generating a random number sequence: determining the parameters inside the set as the numerical values of respective physical quantities, outputting a random number, according to the map with the parameters and the assigned feedback value, and assigning as new feedback value the output random number.

Abstract translation: 一种用于生成随机数序列的方法，其随机特性被先验确定，包括定义参数图，根据图的参数计算使用参数图可获得的随机数序列的熵和Lyapunov指数，以及识别 至少一组熵和Lyapunov指数为正数的参数值，地图无吸引力。 该方法还包括将预先建立的值分配为第一反馈值，并循环地执行以下步骤以产生随机数序列：确定组内的参数作为相应物理量的数值，输出随机数，根据 使用参数和分配的反馈值映射到地图，并将新的反馈值分配给输出随机数。

公开(公告)号：US20040130956A1

公开(公告)日：2004-07-08

申请号：US10701150

申请日：2003-11-04

Applicant: STMicroelectronics S.r.l.

Inventor： Domenico Porto ,  Marco Branciforte ,  Lucio Ticli

IPC: G11C029/00

CPC classification number: G06N99/002 ,  B82Y10/00

Abstract: A hardware quantum gate for running quantum algorithms in a very fast manner exploits the fact that a large number of multiplications required by an entanglement operation of the quantum algorithm provides a null result since only one component per row of the entanglement matrix UF is not a null. The entanglement operation generates an entanglement vector by permuting pairs of opposite components of a linear superposition vector, depending on the value assumed by the function f. More specifically, if function f is null in correspondence to the vector identified by the first (leftmost) n qubits in common with the two nnull1 qubit vectors, in which a pair of opposite components of the superposition vector is referred to, then the corresponding pair of components of the entanglement vector is equal to that of the superposition vector, otherwise it is the opposite.

Abstract translation: 用于以非常快速的方式运行量子算法的硬件量子门利用了这样一个事实：量子算法的纠缠操作所需的大量乘法提供了一个空的结果，因为每行纠缠矩阵UF中只有一个分量不是零 。 缠结操作通过根据函数f所假设的值来排列线性叠加矢量的相对分量对来产生纠缠矢量。 更具体地说，如果函数f对应于与由两个n + 1量子位矢量共同的第一（最左）n个量子位所确定的矢量为零，其中参考叠加矢量的一对相反分量，则 纠缠矢量的对应的一对分量等于叠加矢量的分量，否则是相反的。

公开(公告)号：US20030149511A1

公开(公告)日：2003-08-07

申请号：US10167058

申请日：2002-06-11

Applicant: STMicroelectronics S.r.l.

Inventor： Gianguido Rizzotto ,  Paolo Amato ,  Domenico Porto

IPC: G05B015/00 ,  G05B019/00

CPC classification number: G06N99/002 ,  B82Y10/00

Abstract: A quantum gate performs the superposition operation of a Grover's or of a Deutsch-Jozsa's quantum algorithm in a very fast manner. This is done by performing all multiplications by using logic gates that immediately outputs the result. The superposition operation includes performing the Hadamard rotation over an input set of vectors for producing a set of rotated vectors, and calculating the tensor product of all the rotated vectors for outputting a linear superposition set of vectors. The tensor product of all the rotated vectors is carried out by the logic gates.

Abstract translation: 量子门以非常快的速度执行Grover或Deutsch-Jozsa的量子算法的叠加操作。 这是通过使用立即输出结果的逻辑门执行所有乘法来完成的。 叠加操作包括在矢量的输入集上执行Hadamard旋转以产生一组旋转矢量，以及计算用于输出矢量的线性叠加集合的所有旋转矢量的张量乘积。 所有旋转矢量的张量积由逻辑门执行。

公开(公告)号：US20040162640A1

公开(公告)日：2004-08-19

申请号：US10701160

申请日：2003-11-04

Applicant: STMicroelectronics S.r.l.

Inventor： Marco Branciforte ,  Antonino Calabro ,  Domenico Porto

IPC: G05B015/00

CPC classification number: G06N99/002 ,  B82Y10/00

Abstract: A quantum gate for running a Grover's quantum algorithm using a binary function having a vector basis of n qubits is provided. The quantum gate includes a superposition subsystem, an entanglement subsystem and an interference subsystem. The interference subsystem performs an interference operation on components of entanglement vectors for generating components of output vectors. The interference subsystem performs the interference operation in a very fast manner by using an adder receiving as input signals representing even or odd components of an entanglement vector, and generating a sum signal representing a weighted sum with a scale factor of the even or odd components. The interference subsystem also includes an array of adders each input with a respective signal representative of an even or odd component of an entanglement vector and with the weighted sum signal, and generates a signal representative of an even or odd component of an output vector as a difference between the weighted sum signal and the signal representing an even or odd component of an entanglement vector.

Abstract translation: 提供了使用具有n个量子位的向量基础的二进制函数来运行Grover量子算法的量子门。 量子门包括叠加子系统，纠缠子系统和干扰子系统。 干扰子系统对纠缠矢量的分量进行干扰运算，以产生输出矢量的分量。 干扰子系统通过使用接收作为表示纠缠矢量的偶数或奇数分量的输入信号的加法器以非常快速的方式执行干扰操作，并且产生表示具有偶数或奇数分量的比例因子的加权和的和信号。 干扰子系统还包括加法器阵列，每个加法器输入表示纠缠矢量的偶数或奇数分量的相应信号，并且与加权和信号相加，并且产生表示输出矢量的偶数或奇数分量的信号，作为 加权和信号与表示纠缠矢量的偶数或奇数分量的信号之间的差。

公开(公告)号：US20020133243A1

公开(公告)日：2002-09-19

申请号：US10036300

申请日：2001-12-26

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Abbisso ,  Riccardo Caponetto ,  Olga Diamante ,  Domenico Porto ,  Eusebio Di Cola ,  Luigi Fortuna

IPC: G06F015/18

CPC classification number: G05B11/42 ,  G05B13/027

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network that receives at least one input signal and generates therefrom at least one output signal. The input and output signals are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network. A plurality of such circuits, implementing respective non-integer order controllers can be interconnected in an arrangement wherein any of the integral or differential blocks included in one of these circuits generates a signal which is fed to any of the integral or differential blocks of another circuit in the system.

Abstract translation: 实现非整数阶动态系统的电路包括接收至少一个输入信号并从其产生至少一个输出信号的神经网络。 输入和输出信号通过神经网络的系数与非整数阶积分关系相关。 实现相应的非整数顺序控制器的多个这样的电路可以以这样的布置互连，其中包括在这些电路之一中的积分或差分块中的任何一个产生一个信号，该信号被馈送到另一个电路的任何积分或差分块 在系统中。