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1.发明申请公开(公告)号：US20180151231A1
公开(公告)日：2018-05-31
申请号：US15607636
申请日：2017-05-29
Inventor： Francesca Grande , Francesco La Rosa , Gianbattista Lo Giudice , Giovanni Matranga
CPC classification number: G11C16/16 , G11C16/26 , G11C16/3445
Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
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公开(公告)号：US11183255B1
公开(公告)日：2021-11-23
申请号：US16925059
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Giovanni Matranga , Gianbattista Lo Giudice , Rosario Roberto Grasso , Alberto Jose′ Di Martino
Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.
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Patent Agency Ranking
公开(公告)号：US10147490B2
公开(公告)日：2018-12-04
申请号：US15607636
申请日：2017-05-29
Inventor： Francesca Grande , Francesco La Rosa , Gianbattista Lo Giudice , Giovanni Matranga
Abstract: A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method includes performing a first execution of the memory operation on a set of memory cells by applying a first biasing configuration, storing information associated to the first biasing configuration, and performing a second execution, subsequent to the first execution, of the memory operation on the same set of memory cells by applying a second biasing configuration that is determined according to the stored information associated to the first biasing configuration.
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公开(公告)号：US11328778B2
公开(公告)日：2022-05-10
申请号：US16925104
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Gianbattista Lo Giudice , Giovanni Matranga , Rosario Roberto Grasso , Alberto Jose' Di Martino
Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.
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公开(公告)号：US20220011943A1
公开(公告)日：2022-01-13
申请号：US16925104
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Gianbattista Lo Giudice , Giovanni Matranga , Rosario Roberto Grasso , Alberto Jose' Di Martino
Abstract: A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.
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公开(公告)号：US20240088875A1
公开(公告)日：2024-03-14
申请号：US18451272
申请日：2023-08-17
Applicant: STMicroelectronics S.r.l.
Inventor： Pietro Antonino Coppa , Gianbattista Lo Giudice , Enrico Castaldo , Antonino Conte
CPC classification number: H03K3/0315 , H03K3/011
Abstract: An electronic system is configured to generate a sequential logic signal. The electronic system includes a first ring oscillator including a first plurality of cascaded inverter stages. A combinational logic circuit is configured to generate the sequential logic signal by combining signals at the output terminals of at least two of the inverter stages of the first ring oscillator. The electronic system further includes a second ring oscillator including a second plurality of cascaded inverter stages. A bias current source is configured to supply the inverter stages of the second ring oscillator with a bias current, and a first voltage is generated at the inverter stages of the second ring oscillator. A voltage follower is configured to supply the inverter stages of the first ring oscillator with a second voltage corresponding to the first voltage generated at the inverter stages of the second ring oscillator.
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公开(公告)号：US11495310B2
公开(公告)日：2022-11-08
申请号：US17508775
申请日：2021-10-22
Applicant: STMicroelectronics S.r.l.
Inventor： Giovanni Matranga , Gianbattista Lo Giudice , Rosario Roberto Grasso , Alberto Jose' Di Martino
Abstract: A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.
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