公开(公告)号：US11271555B2

公开(公告)日：2022-03-08

申请号：US16995190

申请日：2020-08-17

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala' ,  Santi Carlo Adamo

IPC: H05B45/10 ,  H03K7/08 ,  G06F13/42

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

公开(公告)号：US20200383189A1

公开(公告)日：2020-12-03

申请号：US16995190

申请日：2020-08-17

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala' ,  Santi Carlo Adamo

IPC: H05B45/37 ,  G06F13/42 ,  H05B45/10 ,  H03K7/08

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

公开(公告)号：US10206258B2

公开(公告)日：2019-02-12

申请号：US15975059

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala' ,  Santi Carlo Adamo

IPC: H05B33/08 ,  H03K7/08

Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.

公开(公告)号：US20180368227A1

公开(公告)日：2018-12-20

申请号：US15975059

申请日：2018-05-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ignazio Cala' ,  Santi Carlo Adamo

IPC: H05B33/08 ,  H03K7/08

CPC classification number: H05B33/0845 ,  H03K3/017 ,  H03K7/08 ,  H05B33/0815

Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.