Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol
    1.
    发明申请
    Start detection circuit, stop detection circuit and circuit for the detection of data transmitted according to the IIC protocol 有权
    启动检测电路,停止检测电路和电路,用于检测根据IIC协议传输的数据

    公开(公告)号:US20040010728A1

    公开(公告)日:2004-01-15

    申请号:US10438289

    申请日:2003-05-13

    CPC classification number: H03K5/19 H03K5/1252 H04L7/044

    Abstract: A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

    Abstract translation: 启动检测电路和停止检测电路根据IIC协议检测与时钟信号相关联的数据信号中的启动条件和停止条件。 启动检测电路包括:当检测到数据信号的后沿时产生第一复位信号的第一检测器; 计数器,当接收到第一复位信号时计数参考信号的脉冲,并且当计数的脉冲数达到预定数量时产生使能信号; 当检测到时钟信号的后沿时,存储启用信号的第二检测器。 停止检测电路包括第三检测器,当在检测到时钟信号的前沿之后检测到数据信号的前沿时产生停止信号。

    Microcontroller device for complex processing procedures and corresponding interrupt management process
    2.
    发明申请
    Microcontroller device for complex processing procedures and corresponding interrupt management process 审中-公开
    用于复杂处理程序的微控制器和相应的中断管理过程

    公开(公告)号:US20040230319A1

    公开(公告)日:2004-11-18

    申请号:US10783712

    申请日:2004-02-20

    CPC classification number: G06F9/325 G06F9/3861 G06F13/24

    Abstract: A microcontroller device in which complex processing procedures to be executed iteratively are implemented in a hardware manner by finite state machines, the deice including a module for managing the processing procedures and an interrupt managing module, and a set of registers for enabling interruption of execution in the module, for managing the processing procedures and transfer of control to the interrupt manager, as well as for enabling restoration of the control to the manager of the processing procedures. The registers store information regarding the type of interrupt and the state on which it intervenes. Selection information is derived from the contents of the registers to establish whether the interrupt operates on a standard instruction or else on an iterative procedure, and in order to command operation of the control unit accordingly.

    Abstract translation: 一种微控制器装置,其中迭代执行的复杂处理程序以硬件方式由有限状态机实现,该模块包括用于管理处理过程的模块和一个中断管理模块,以及一组用于使执行中断的寄存器 该模块用于管理处理过程并将控制传递给中断管理器,以及用于使管理者能够恢复对处理过程的控制。 寄存器存储有关中断类型和介入状态的信息。 从寄存器的内容中导出选择信息,以确定中断是否以标准指令进行操作,或者在迭代过程中操作,并且相应地指令控制单元的操作。

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