公开(公告)号：US20020008299A1

公开(公告)日：2002-01-24

申请号：US09853833

申请日：2001-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi

IPC: H01L029/00 ,  H01L021/331

CPC classification number: H01L21/763

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract translation: 一种具有衬底的集成器件，其中已经形成了掩埋层和外延区域，以及隔离结构，其适于限定用于将集成器件的部件集成在其中的多个隔离阱，该隔离结构包括多个介电绝缘区域或电介质 沟槽填充有导电材料以形成多个接触区域到器件的掩埋区域，掩埋区域尤其包括衬底和掩埋层。

公开(公告)号：US20040021169A1

公开(公告)日：2004-02-05

申请号：US10442646

申请日：2003-05-21

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi

IPC: H01L029/76

CPC classification number: H01L29/78612 ,  H01L21/76283 ,  H01L29/0692 ,  H01L29/1087

Abstract: The integrated structure and process is effective to form, in a dielectrically insulated well, a MOS component including respective drain and source regions of a first conductivity type as well as a gate region. The integrated structure includes a cut-off layer of the second conductivity type effective to surround only the source region. The cut-off layer is self-aligned by the gate region.

Abstract translation: 该集成结构和工艺有效地在介电绝缘的阱中形成包括第一导电类型和栅极区的各自的漏极和源极区的MOS分量。 该集成结构包括仅仅围绕源极区域的第二导电类型的截止层。 截止层由栅极区域自对准。

公开(公告)号：US20030060012A1

公开(公告)日：2003-03-27

申请号：US10213016

申请日：2002-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi

IPC: H01L021/336

CPC classification number: H01L21/76208 ,  H01L21/761 ,  H01L27/088

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region comprising at least one P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, comprising at least one trench filled with dielectric material. A method of manufacturing the electronic power device includes forming a silicon oxide-filled trench by the following steps: forming, in the substrate, a plurality of small trenches having predetermined widths and being delimited by a corresponding plurality of semiconductor material walls having second predetermined widths; and oxidizing the semiconductor by a thermal process directed to oxidize the walls and produce a single trench.

公开(公告)号：US20030205780A1

公开(公告)日：2003-11-06

申请号：US10420386

申请日：2003-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi

IPC: H01L029/00

CPC classification number: H01L21/76208 ,  H01L21/761 ,  H01L27/0802

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

公开(公告)号：US20030137009A1

公开(公告)日：2003-07-24

申请号：US10268054

申请日：2002-10-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Salvatore Leonardi

IPC: H01L023/62 ,  H01L021/8238

CPC classification number: H01L29/74 ,  H01L21/76264 ,  H01L27/0255 ,  H01L27/1203

Abstract: A protection structure against electrostatic discharges for a semiconductor electronic devicethat is integrated inside a well is disclosed, wherein the well is formed on a SOI substrateand isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.

Abstract translation: 公开了一种防止半导体电子设备的静电放电的保护结构，其中阱被形成在SOI衬底上，并且被掩埋氧化物层和隔离结构介电隔离，该隔离结构又包括至少介电层 填充填充材料的沟槽。 有利地，保护结构形成在隔离结构处。

公开(公告)号：US20040119137A1

公开(公告)日：2004-06-24

申请号：US10729721

申请日：2003-12-05

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi ,  Roberto Modica

IPC: H01L029/00

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract translation: 一种电阻结构，其集成在半导体衬底中并且具有完全被介电区域包围的适当掺杂的多晶硅区域，使得该电阻结构与联合地集成在该半导体衬底中的其它部件电隔离。

公开(公告)号：US20040026761A1

公开(公告)日：2004-02-12

申请号：US10444102

申请日：2003-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi ,  Roberto Modica ,  Giuseppe Arena

IPC: H01L029/00

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Abstract translation: 通过在其中集成介电沟槽结构，在硅层中形成介电绝缘结构。 电介质沟槽结构限定了将半导体器件集成在其中的绝缘阱。 电介质沟槽结构在完全被电介质区域包围的中空区域上。 电介质区域也形成电介质沟槽结构的侧绝缘体。 电介质沟槽结构被多个点中断，以限定用于绝缘阱的多个侧支撑区域。