公开(公告)号：US20040026761A1

公开(公告)日：2004-02-12

申请号：US10444102

申请日：2003-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Leonardi ,  Roberto Modica ,  Giuseppe Arena

IPC: H01L029/00

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: A dielectric insulation structure is formed in a silicon layer by integrating a dielectric trench structure therein. The dielectric trench structure defines an insulation well where semiconductor devices are to be integrated therein. The dielectric trench structure is on a hollow region that is completely surrounded by a dielectric area. The dielectric area also forms the side insulation of the dielectric trench structure. The dielectric trench structure is interrupted by a plurality of points to define a plurality of side support regions for the insulation well.

Abstract translation: 通过在其中集成介电沟槽结构，在硅层中形成介电绝缘结构。 电介质沟槽结构限定了将半导体器件集成在其中的绝缘阱。 电介质沟槽结构在完全被电介质区域包围的中空区域上。 电介质区域也形成电介质沟槽结构的侧绝缘体。 电介质沟槽结构被多个点中断，以限定用于绝缘阱的多个侧支撑区域。

公开(公告)号：US20010023094A1

公开(公告)日：2001-09-20

申请号：US09752149

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Giuseppe D'Arrigo ,  Corrado Spinella ,  Salvatore Coffa ,  Giuseppe Arena ,  Marco Camalleri

IPC: H01L021/8238

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76286

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract translation: 提供一种制造绝缘体上硅（SOI）晶片的方法，该方法包括其中埋有掺杂区的单晶硅衬底。 该方法包括形成从衬底的表面延伸到掺杂掩埋区的多个沟槽状开口，并且选择性地蚀刻穿过多个沟槽状开口以将掺杂掩埋区改变为多孔硅区。 多孔硅区域被氧化以获得用于SOI晶片的绝缘区域。