公开(公告)号：US20180341791A1

公开(公告)日：2018-11-29

申请号：US15945177

申请日：2018-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda

IPC: G06F21/85 ,  G06F13/40

Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.

公开(公告)号：US11144678B2

公开(公告)日：2021-10-12

申请号：US15916067

申请日：2018-03-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda ,  Layachi Daineche

IPC: H04L9/00 ,  G06F21/85 ,  G06F21/76 ,  G06F21/60 ,  G06F13/40 ,  G06F21/71

Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.

公开(公告)号：US20210357015A1

公开(公告)日：2021-11-18

申请号：US16874020

申请日：2020-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Pasquale Butta' ,  Sergio Abenda

IPC: G06F1/3234 ,  H03K3/037

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

公开(公告)号：US11803226B2

公开(公告)日：2023-10-31

申请号：US16874020

申请日：2020-05-14

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Pasquale Butta′ ,  Sergio Abenda

IPC: G06F1/3234 ,  H03K3/037 ,  G06F1/3296

CPC classification number: G06F1/325 ,  G06F1/3243 ,  H03K3/037

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

公开(公告)号：US10891399B2

公开(公告)日：2021-01-12

申请号：US15945177

申请日：2018-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda

IPC: G06F21/85 ,  G06F15/78 ,  G06F21/74 ,  G06F21/72 ,  G06F13/40

Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.