公开(公告)号：US11144678B2

公开(公告)日：2021-10-12

申请号：US15916067

申请日：2018-03-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda ,  Layachi Daineche

IPC: H04L9/00 ,  G06F21/85 ,  G06F21/76 ,  G06F21/60 ,  G06F13/40 ,  G06F21/71

Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.

公开(公告)号：US11143701B2

公开(公告)日：2021-10-12

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US11269986B2

公开(公告)日：2022-03-08

申请号：US16660243

申请日：2019-10-22

Applicant: STMicroelectronics (Grand Ouest) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Berthelot ,  Layachi Daineche

IPC: G06F21/00 ,  G06F21/44

Abstract: A memory stores a program to be executed by a microprocessor. The program includes a first program part and a second program part. An authenticator is configured to authenticate the program and includes a module that is external to the microprocessor and configured to authenticate said first program part when the microprocessor is inactive. The authenticator further activates the microprocessor to execute the first program part and authenticate said second program part using instructions of the first program part if the module has authenticated the first program part. The microprocessor then executes the second program part if the microprocessor has authenticated said second program part.

公开(公告)号：US20200319247A1

公开(公告)日：2020-10-08

申请号：US16909696

申请日：2020-06-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US20190107576A1

公开(公告)日：2019-04-11

申请号：US16155953

申请日：2018-10-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/317 ,  G06F11/36 ,  G06F9/4401 ,  G06F11/22

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

公开(公告)号：US11055237B2

公开(公告)日：2021-07-06

申请号：US16594210

申请日：2019-10-07

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Layachi Daineche ,  Xavier Chbani ,  Nadia Van-Den-Bossche

IPC: G06F21/79 ,  G06F12/14 ,  G06F9/4401 ,  G06F21/62

Abstract: In a non-volatile memory of a microcontroller, first information representative of a value selected among at least four values is stored. Furthermore, for each of a plurality of areas of the memory, second information representative of a type selected among two types is also stored. Access to each of the areas is conditioned according to the selected value and to the type of the area.

公开(公告)号：US10705141B2

公开(公告)日：2020-07-07

申请号：US16155953

申请日：2018-10-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.