公开(公告)号：US10891399B2

公开(公告)日：2021-01-12

申请号：US15945177

申请日：2018-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda

IPC: G06F21/85 ,  G06F15/78 ,  G06F21/74 ,  G06F21/72 ,  G06F13/40

Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.

公开(公告)号：US10788870B2

公开(公告)日：2020-09-29

申请号：US16405086

申请日：2019-05-07

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Gaetano Di Stefano ,  Mirko Dondini

IPC: G06F1/24 ,  G06F11/267 ,  H03K3/037

Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.

公开(公告)号：US10236066B2

公开(公告)日：2019-03-19

申请号：US15692158

申请日：2017-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Gaetano Di Stefano ,  Roberto Sebastiano Ruggirello

IPC: G11C16/10 ,  G11C8/20 ,  G11C13/00 ,  G06F12/02 ,  G06F12/0868

Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.

公开(公告)号：US20190354152A1

公开(公告)日：2019-11-21

申请号：US16405086

申请日：2019-05-07

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Gaetano Di Stefano ,  Mirko Dondini

IPC: G06F1/24 ,  G06F11/267 ,  H03K3/037

Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.

公开(公告)号：US20180341791A1

公开(公告)日：2018-11-29

申请号：US15945177

申请日：2018-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda

IPC: G06F21/85 ,  G06F13/40

Abstract: A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.

公开(公告)号：US11144678B2

公开(公告)日：2021-10-12

申请号：US15916067

申请日：2018-03-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mirko Dondini ,  Gaetano Di Stefano ,  Sergio Abenda ,  Layachi Daineche

IPC: H04L9/00 ,  G06F21/85 ,  G06F21/76 ,  G06F21/60 ,  G06F13/40 ,  G06F21/71

Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.

公开(公告)号：US09823965B2

公开(公告)日：2017-11-21

申请号：US15080307

申请日：2016-03-24

Applicant: STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Michele Alessandro Carrano ,  Gaetano Di Stefano ,  Antonin Fried

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1044 ,  G11C29/52

Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.