公开(公告)号：US20150194357A1

公开(公告)日：2015-07-09

申请号：US14290064

申请日：2014-05-29

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom LEE ,  Sang-Hyun KANG ,  Soo-Chul KIM ,  Hong-Joon MOON ,  Jun-Seok LEE

IPC: H01L21/66 ,  G01R31/26 ,  H01L27/12

CPC classification number: H01L22/32 ,  G09G3/006 ,  G09G3/3614 ,  G09G2300/0426

Abstract: A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.

Abstract translation: 显示基板包括被配置为接收第一栅极时钟的第一栅极线，与第一栅极线相邻并被配置为接收第二栅极时钟的第二栅极线，被配置为传送根据第二栅极时钟反转的第一数据信号的第一数据线 第一栅极时钟和第二栅极时钟，其中第一数据信号具有第一极性，第二数据线被配置为传送根据第一栅极时钟和第二栅极时钟反转的第二数据信号，其中第二数据信号具有 第二极性与第一极性不同，第一像素包括电连接到第一栅极线和第一数据线的第一高子像素，以及电连接到第一栅极线和第二数据线的第一低子像素。

公开(公告)号：US20150228664A1

公开(公告)日：2015-08-13

申请号：US14325110

申请日：2014-07-07

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom LEE ,  Sang-Hyun KANG ,  Soo-Chul KIM ,  Hong-Joon MOON ,  Jun-Seok LEE

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  H01L29/786

CPC classification number: H01L27/1259 ,  G02F1/136227 ,  G02F1/136259 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L21/76894 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L2251/568

Abstract: A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.

Abstract translation: 显示基板包括第一开关元件，设置在第一开关元件上的有机层，设置在有机层上的封盖层和覆盖第一发射孔的覆盖电极。 第一开关元件电连接到沿第一方向延伸的栅极线，沿与第一方向交叉的第二方向延伸的数据线和邻近数据线设置的像素电极。 封盖层包括第一发射孔。 覆盖电极与栅极线重叠为第一宽度。 覆盖电极作为第二宽度与第一开关元件重叠。 第二宽度小于第一宽度。

公开(公告)号：US20140347349A1

公开(公告)日：2014-11-27

申请号：US14459140

申请日：2014-08-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwi-Hyun KIM ,  Jang-Soo KIM ,  Hyeong-Jun JIN ,  Soo-Chul KIM ,  Kyoung-Hae MIN

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/04 ,  G11C19/28

Abstract: In one embodiment, a display panel includes a substrate and a gate driver disposed on the substrate. The gate driver comprises a wiring unit which receives signals and a circuit unit which outputs driving signals in response to the signals received from the wiring unit. The circuit unit comprises a shift register and a shift register wiring connected to the shift register. The wiring unit comprises first through n-th signal lines (n is a natural number greater than two) arranged sequentially adjacent to the shift register. The first line is located farthest from the shift register and the n-th signal line is closest from the shift register. Further, the first signal line is electrically connected to the shift register by a first connection line that comprises a first contact portion connected to the first signal line and a second contact portion connected to the shift resistor wiring.

Abstract translation: 在一个实施例中，显示面板包括设置在基板上的基板和栅极驱动器。 栅极驱动器包括接收信号的布线单元和响应于从布线单元接收的信号而输出驱动信号的电路单元。 电路单元包括移位寄存器和连接到移位寄存器的移位寄存器布线。 布线单元包括顺序地与移位寄存器相邻布置的第一至第n信号线（n是大于2的自然数）。 第一行位于离移位寄存器最远的位置，第n条信号线最靠近移位寄存器。 此外，第一信号线通过包括连接到第一信号线的第一接触部分和连接到换档电阻器接线的第二接触部分的第一连接线电连接到移位寄存器。