公开(公告)号：US20150194357A1

公开(公告)日：2015-07-09

申请号：US14290064

申请日：2014-05-29

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom LEE ,  Sang-Hyun KANG ,  Soo-Chul KIM ,  Hong-Joon MOON ,  Jun-Seok LEE

IPC: H01L21/66 ,  G01R31/26 ,  H01L27/12

CPC classification number: H01L22/32 ,  G09G3/006 ,  G09G3/3614 ,  G09G2300/0426

Abstract: A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.

Abstract translation: 显示基板包括被配置为接收第一栅极时钟的第一栅极线，与第一栅极线相邻并被配置为接收第二栅极时钟的第二栅极线，被配置为传送根据第二栅极时钟反转的第一数据信号的第一数据线 第一栅极时钟和第二栅极时钟，其中第一数据信号具有第一极性，第二数据线被配置为传送根据第一栅极时钟和第二栅极时钟反转的第二数据信号，其中第二数据信号具有 第二极性与第一极性不同，第一像素包括电连接到第一栅极线和第一数据线的第一高子像素，以及电连接到第一栅极线和第二数据线的第一低子像素。

公开(公告)号：US20150364495A1

公开(公告)日：2015-12-17

申请号：US14610358

申请日：2015-01-30

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Hwa PARK ,  Do-Yeong PARK ,  Jun-Seok LEE ,  Ki-Pyo HONG

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/441 ,  H01L23/528 ,  H01L21/02 ,  H01L21/465 ,  H01L21/469 ,  H01L21/4757 ,  H01L29/786 ,  H01L21/4763

CPC classification number: H01L27/124 ,  H01L21/465 ,  H01L21/469 ,  H01L21/47573 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869

Abstract: A display substrate includes a gate line extending in a first direction, a floating electrode disposed on the same layer as the gate line, and a data line. Opposite ends of the floating electrode are electrically connected with the data line. The floating electrode extends in a second direction that crosses the first direction. The data line includes a recess disposed adjacent to the gate line. The data line overlaps with the floating electrode and also extends in the second direction.

Abstract translation: 显示基板包括沿第一方向延伸的栅极线，设置在与栅极线相同的层上的浮置电极和数据线。 浮动电极的相对端与数据线电连接。 浮动电极沿与第一方向交叉的第二方向延伸。 数据线包括邻近栅极线布置的凹槽。 数据线与浮动电极重叠并且在第二方向上延伸。

公开(公告)号：US20150228664A1

公开(公告)日：2015-08-13

申请号：US14325110

申请日：2014-07-07

Applicant: Samsung Display Co., LTD.

Inventor： Hong-Beom LEE ,  Sang-Hyun KANG ,  Soo-Chul KIM ,  Hong-Joon MOON ,  Jun-Seok LEE

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  H01L29/786

CPC classification number: H01L27/1259 ,  G02F1/136227 ,  G02F1/136259 ,  G02F2001/136218 ,  G02F2001/136222 ,  H01L21/76894 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L2251/568

Abstract: A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.

Abstract translation: 显示基板包括第一开关元件，设置在第一开关元件上的有机层，设置在有机层上的封盖层和覆盖第一发射孔的覆盖电极。 第一开关元件电连接到沿第一方向延伸的栅极线，沿与第一方向交叉的第二方向延伸的数据线和邻近数据线设置的像素电极。 封盖层包括第一发射孔。 覆盖电极与栅极线重叠为第一宽度。 覆盖电极作为第二宽度与第一开关元件重叠。 第二宽度小于第一宽度。

公开(公告)号：US20150109554A1

公开(公告)日：2015-04-23

申请号：US14307705

申请日：2014-06-18

Applicant: Samsung Display Co., Ltd.

Inventor： Hong Beom LEE ,  Jun-Seok LEE

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/1362 ,  G02F2001/133776

Abstract: A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括：在一个方向上延伸并且彼此平行的第一至第三栅极线; 与第一至第三栅极线绝缘并与之相交的数据线; 连接到第一栅极线和数据线的第一薄膜晶体管; 连接到第二栅极线的第二薄膜晶体管和第一薄膜晶体管的输出端子; 连接到第三栅极线和数据线的第三薄膜晶体管; 连接到第二栅极线的第四薄膜晶体管和第三薄膜晶体管的输出端子; 以及分别连接到第一至第四薄膜晶体管的第一至第四子像素电极。