公开(公告)号：US11030952B2

公开(公告)日：2021-06-08

申请号：US16734709

申请日：2020-01-06

Applicant: Samsung Display Co., LTD.

Inventor： Jun-Hyun Park ,  Young-Wan Seo ,  An-Su Lee ,  Bo-Yong Chung ,  Kang-Moon Jo ,  Chong-Chul Chai

IPC: G09G3/3233 ,  H01L51/52 ,  G09G3/3258 ,  H01L27/32

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.

公开(公告)号：US10540927B2

公开(公告)日：2020-01-21

申请号：US15862944

申请日：2018-01-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun-Hyun Park ,  Young-Wan Seo ,  An-Su Lee ,  Bo-Yong Chung ,  Kang-Moon Jo ,  Chong-Chul Chai

IPC: G09G3/3233 ,  H01L51/52 ,  G09G3/3258 ,  H01L27/32

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.

公开(公告)号：US10217414B2

公开(公告)日：2019-02-26

申请号：US15349284

申请日：2016-11-11

Applicant: Samsung Display Co., Ltd

Inventor： Jun-Hyun Park ,  Sung-Hwan Kim ,  Kyoung-Ju Shin ,  Sang-Uk Lim ,  Yang-Hwa Choi

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3291

Abstract: An emission control driver includes a plurality of stages configured to output a plurality of emission control signals, respectively. Each stage includes an input circuit for receiving a previous emission control signal from one of previous stages or a vertical start signal, and configured to control a voltage of a first node and a voltage of a second node in response to a first clock signal; a stabilizing circuit for stabilizing the voltage of the first node in response to the voltage of the second node and a second clock signal; a voltage adjusting circuit connected between the second node and a third node, configured for boosting the voltage of the second node, and controlling the boosted voltage of the second node; and an output circuit configured to control an emission control signal in response to the voltage of the first node and a voltage of the third node.

公开(公告)号：US10204544B2

公开(公告)日：2019-02-12

申请号：US15350917

申请日：2016-11-14

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung-Hwan Kim ,  Jun-Hyun Park ,  Kyoung-Ju Shin

IPC: G09G3/20 ,  G09G3/3266 ,  G11C19/28 ,  G09G3/3233

Abstract: A display panel driver includes a plurality of stages. An N-th stage of the plurality of stages is configured to output a scan signal and an emission signal synchronized with each other based on a first power voltage, a second power voltage, and at least one clock signal. N is a natural number.

公开(公告)号：US10102803B2

公开(公告)日：2018-10-16

申请号：US15645567

申请日：2017-07-10

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-Hyun Park ,  An-Su Lee ,  Bo-Yong Chung ,  Chong-Chul Chai

IPC: G09G3/00 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3275

Abstract: A display apparatus includes a plurality of pixels. Each pixel includes a first capacitor connected between a first voltage line receiving a driving signal and a first node; a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal, and a second electrode connected to a second node; an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal; a second capacitor connected between an m-th data line and the second node; a second transistor comprising a control electrode connected to an n-th gate line, a first electrode connected to the first node, and a second electrode connected to the second node;and a third transistor comprising a control electrode connected to an n-th scan line, a first electrode connected to the first voltage line, and a second electrode connected to the second node.

公开(公告)号：US09947274B2

公开(公告)日：2018-04-17

申请号：US15299250

申请日：2016-10-20

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-Hyun Park ,  Sung-Hwan Kim ,  Kyoung-Ju Shin ,  Sang-Uk Lim ,  Yang-Hwa Choi

IPC: G09G3/32 ,  G09G3/3266 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3291

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver includes a plurality of stages outputting a plurality of gate output signals, respectively. Each stage includes a first input circuit applying an input signal to a first node in response to a first clock signal, a second input circuit applying the first clock signal to a second node in response to a voltage of the first node, a first output circuit controlling a gate output signal to a first logic level in response to the voltage of the first node, a second output circuit controlling the gate output signal to a second logic level in response to a voltage of the second node, and a leakage current blocking circuit applying a first power voltage corresponding to the first logic level to the first input circuit in response to the voltage of the first node.

公开(公告)号：US12232377B2

公开(公告)日：2025-02-18

申请号：US17623239

申请日：2019-11-29

Applicant: Samsung Display Co., LTD.

Inventor： Jun-Hyun Park ,  Dong-Woo Kim ,  An-Su Lee ,  Kang-Moon Jo

IPC: H10K59/131

Abstract: A display device including a substrate, a first upper power line, a conductive member, a protective insulating layer, an upper connection member, and a sub-pixel structure. The upper connection member is disposed in a first pad area and a first peripheral area on a planarization layer, and electrically connects the first upper power line and the conductive member through a first contact hole, which is formed in the protective insulating layer and the planarization layer located on the conductive member, and a second contact hole, which is formed in the protective insulating layer and the planarization layer located on the first upper power line.

公开(公告)号：US10283054B2

公开(公告)日：2019-05-07

申请号：US15696734

申请日：2017-09-06

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jun-Hyun Park ,  An-Su Lee ,  Ji-Hye Lee ,  Bo-Yong Chung ,  Kang-Moon Jo ,  Chong-Chul Chai

IPC: G09G3/3266 ,  G09G3/3258 ,  G09G3/3291

Abstract: A pixel includes first to fourth transistors and a driving transistor. The first transistor is connected between a data line and a first node and has a gate electrode to receive a scan signal. The driving transistor is connected between the first node and a second node and has a gate electrode connected to a third node. The second transistor is connected between the second and third nodes and has a gate electrode to receive the scan signal. The third transistor is connected between first power and the first node and has a gate electrode to receive an emission signal. The fourth transistor is connected between the first and second nodes and has a gate electrode to receive an initialization signal. An organic light emitting diode is connected between the second node and second power. A storage capacitor is connected between the first power and third node.

公开(公告)号：US20170294165A1

公开(公告)日：2017-10-12

申请号：US15299250

申请日：2016-10-20

Applicant: Samsung Display Co., Ltd.

Inventor： Jun-Hyun Park ,  Sung-Hwan Kim ,  Kyoung-Ju Shin ,  Sang-Uk Lim ,  Yang-Hwa Choi

IPC: G09G3/3266 ,  G09G3/3291 ,  G09G3/3233 ,  G09G3/325

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/325 ,  G09G3/3291 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0214 ,  G11C19/28

Abstract: A gate driver includes a plurality of stages outputting a plurality of gate output signals, respectively. Each stage includes a first input circuit applying an input signal to a first node in response to a first clock signal, a second input circuit applying the first clock signal to a second node in response to a voltage of the first node, a first output circuit controlling a gate output signal to a first logic level in response to the voltage of the first node, a second output circuit controlling the gate output signal to a second logic level in response to a voltage of the second node, and a leakage current blocking circuit applying a first power voltage corresponding to the first logic level to the first input circuit in response to the voltage of the first node.

公开(公告)号：US11328667B2

公开(公告)日：2022-05-10

申请号：US17313471

申请日：2021-05-06

Applicant: Samsung Display Co., LTD.

Inventor： Jun-Hyun Park ,  Young-Wan Seo ,  An-Su Lee ,  Bo-Yong Chung ,  Kang-Moon Jo ,  Chong-Chul Chai

IPC: G09G3/3233 ,  H01L51/52 ,  G09G3/3258 ,  H01L27/32

Abstract: A display panel driver drives pixels based on first power having at least three voltage levels, second power having a constant voltage, and third power having two voltage levels. Each pixel includes a first transistor connected between first and second nodes and including a gate electrode to receive a scan signal, a second transistor connected between the second node and a third node in series with the first transistor and including a gate electrode to receive the third power, and a driving transistor connected between a source of the first power and the third node and including a gate electrode connected to the first electrode to control a driving current for an organic light emitting diode. A first capacitor is connected between a source of the third power and the first node, and a second capacitor is connected between the second node and one of the data lines.