Abstract:
The present invention relates to a display apparatus with pixels, wherein each pixel includes a switching device, a micro-electro-mechanical system (MEMS), and a gray scale control device. The switching device can be connected to a gate line and a data line to output a corresponding data signal in response to a gate signal. The MEMS may be connected to an output electrode of the switching device to transmit or block light in response to the corresponding data signal. The gray scale control device may be coupled to the output electrode of the switching device to control a time interval during which the corresponding data signal is applied to the MEMS. Accordingly, each pixel may display a desired gray scale.
Abstract:
An image processing part includes an edge enhancing part, an artifact detecting part and a compensating part. The edge enhancing part emphasizes an edge portion of an object in input image data. The artifact detecting part detects a corner outlier artifact at an area adjacent to the edge portion of the object. The compensating part compensates the corner outlier artifact. Accordingly, the edge portion of the object may be enhanced and the corner outlier artifact is decreased so that the display quality may be improved.
Abstract:
A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.
Abstract:
A gate driver includes a plurality of stages outputting a plurality of gate output signals, respectively. Each stage includes a first input circuit applying an input signal to a first node in response to a first clock signal, a second input circuit applying the first clock signal to a second node in response to a voltage of the first node, a first output circuit controlling a gate output signal to a first logic level in response to the voltage of the first node, a second output circuit controlling the gate output signal to a second logic level in response to a voltage of the second node, and a leakage current blocking circuit applying a first power voltage corresponding to the first logic level to the first input circuit in response to the voltage of the first node.
Abstract:
A display panel includes a display area including a gate line and a data line, a gate driver integrated on a substrate and connected to one end of the gate line, the gate driver including a plurality of a stage, a signal line connected to the stages; and a blocking member disposed on the signal line and overlapped with the signal line, the blocking member including a plurality of an opening.
Abstract:
A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other.
Abstract:
A liquid crystal display panel, including a unit pixel including a first substrate having a first alignment film, a second substrate having a second alignment film spaced apart from and facing the first alignment film, and a liquid crystal layer interposed between the first alignment film and the second alignment film; and first and second adjacent domains, each of which includes a domain boundary region defining part of an area between the adjacent domains, and a normal-luminance region adjacent to the domain boundary region, wherein pretilt angles of liquid crystal molecules near the first alignment film in the domain boundary regions are greater than pretilt angles of liquid crystal molecules near the first alignment film in the normal-luminance regions.
Abstract:
A luminance adjustment part includes a luminance determination part and a data compensation part. The luminance determination part may determine a control value for controlling luminance of a backlight assembly using linear image data that has a linear luminance profile and is generated by performing a de-gamma process on a first copy of input image data that has a nonlinear luminance profile. The compensation part may compensate pixel data that corresponds to pixels of a display panel using the control value, the pixel data being generated using a second copy of the input image data. Thus, color distortion of a displayed image as perceived by a viewer may be minimized when power consumption of a display apparatus that includes the display panel is decreased.
Abstract:
A method of driving a display panel includes determining a driving mode including a two-dimensional (“2D”) mode and a three-dimensional (“3D”) mode and charging a voltage which varies according to the driving mode to at least one subpixel in a unit pixel of the display panel.
Abstract:
A display device includes: pixels to emit light of various intensity in accordance with driving signals; data lines to communicate the driving signals to the pixels; scan lines to communicate scan signals to select at least one of the pixels to receive the driving signals; a first power supply to supply at least one driving voltage to the pixels; and a second power supply including an initial voltage terminal to supply an initial voltage to the pixels. The at least one pixel includes: a driving transistor connected between the first power supply and an anode electrode of an organic light emitting diode, a third transistor including an oxide transistor, the third transistor having a first electrode connected to the initial voltage terminal, a second electrode connected to the anode electrode, and first and second gate electrodes, each of which is connected to one of the scan lines, and a fourth transistor including a poly-silicon transistor, the fourth transistor having a first electrode connected to the first power supply, and a second electrode connected to a second electrode of the driving transistor.