METHOD FOR GENERATING LEARNING MODEL FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE AND APPARATUS FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE

    公开(公告)号:US20240402619A1

    公开(公告)日:2024-12-05

    申请号:US18404626

    申请日:2024-01-04

    Abstract: An apparatus for predicting a structure of a semiconductor device, the apparatus includes: at least one processor; a storage configured to store a learned model configured to predict the structure of the semiconductor device; and a memory configured to store at least one code, and at least one processor operatively connected to the memory and configured to execute the at least one code to: input non-destructive metrology data measured from the semiconductor device into the learned model, and predict the structure of the semiconductor device, based on the learned model, wherein the learned model is trained with training data including first data which is non-destructive metrology data and second data which is structural metrology data as reference data of the first data, and wherein the training data is refined based on a similarity of the training data in a space having a first axis corresponding to the first data and a second axis corresponding to the second data as reference axes.

    METHOD OF GENERATING DEVICE STRUCTURE PREDICTION MODEL AND DEVICE STRUCTURE SIMULATION APPARATUS

    公开(公告)号:US20230062430A1

    公开(公告)日:2023-03-02

    申请号:US17890557

    申请日:2022-08-18

    Abstract: A device structure simulation apparatus includes a memory storing a device structure simulation program and a processor configured to execute the device structure simulation program stored in the memory. By executing the device structure simulation program, the device structure simulation apparatus is further configured to receive spectrum data of a target device, generate an input data set by performing preprocessing on the spectrum data, and train a model based on the input data set such that the model is configured to predict a structure of the target device. The preprocessing including selecting a certain basis function based on the spectrum data and separating the spectrum data into sets of certain basis functions, and the model includes at least one sub model.

    SEMICONDUCTOR WAFER FAULT ANALYSIS SYSTEM AND OPERATION METHOD THEREOF

    公开(公告)号:US20200175665A1

    公开(公告)日:2020-06-04

    申请号:US16599733

    申请日:2019-10-11

    Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

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