公开(公告)号：US11342283B2

公开(公告)日：2022-05-24

申请号：US16810091

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.

公开(公告)号：US20230130436A1

公开(公告)日：2023-04-27

申请号：US17743971

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/498

Abstract: A semiconductor package includes a package substrate having a first surface and a second surface opposite to the first surface, and including a plurality of bonding pads exposed to the first surface and a plurality of solder bumps respectively disposed on the bonding pads, and at least one semiconductor device arranged on the package substrate. Each of the solder bumps includes a bump body disposed on the bonding pad, a plurality of bonding particles provided inside the bump body to be adjacent to the bonding pad, and a first metal compound layer provided to surround the bonding particles and having a protrusion structure for strengthening adhesion with the bonding pad.

公开(公告)号：US11749630B2

公开(公告)日：2023-09-05

申请号：US17199674

申请日：2021-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Haeseong Jeong ,  Sangsu Ha

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/562

Abstract: A semiconductor chip includes a back end of line (BEOL) structure on a first surface of the semiconductor substrate and including a conductive connection structure and an interlayer insulating layer covering the conductive connection structure, a conductive reinforcing layer arranged on the BEOL structure, a cover insulating layer covering the conductive reinforcing layer, an under bump metal (UBM) layer including a plurality of pad connection portions connected to the conductive reinforcing layer through openings in the cover insulating layer, and a plurality of first connection bumps arranged on the plurality of pad connection portions of the UBM layer, electrically connected to one another through the conductive reinforcing layer, and located to overlap the conductive reinforcing layer. The conductive reinforcing layer has a plate shape and extends parallel to the first surface of the semiconductor substrate.

公开(公告)号：US11784139B2

公开(公告)日：2023-10-10

申请号：US17750903

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungwook Kim ,  Ayoung Kim ,  Seongwon Jeong ,  Sangsu Ha

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/3512

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.