专利检索 cpc:"H01L2924/3512" 第 1 页

1.

发明授权
Hermetic package for high CTE mismatch 有权

公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

申请人： Qorvo US, Inc.

发明人： Dylan Murdock

IPC分类号： H01L23/31 , H01L23/04 , H01L23/10 , H01L23/29 , H01L23/00 , H01L23/373

CPC分类号： H01L23/3142 , H01L23/04 , H01L23/10 , H01L23/291 , H01L23/315 , H01L23/3736 , H01L24/48 , H01L24/49 , H01L2224/48225 , H01L2224/49176 , H01L2924/01042 , H01L2924/01074 , H01L2924/0132 , H01L2924/01403 , H01L2924/05432 , H01L2924/15153 , H01L2924/1517 , H01L2924/15747 , H01L2924/15763 , H01L2924/15787 , H01L2924/16747 , H01L2924/1676 , H01L2924/173 , H01L2924/17747 , H01L2924/1776 , H01L2924/3512

摘要： The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

2.

发明公开
PAD AND PACKAGE INCLUDING SAME 审中-公开

公开(公告)号：US20240321788A1

公开(公告)日：2024-09-26

申请号：US18439349

申请日：2024-02-12

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wenjun WANG

IPC分类号： H01L23/00 , H04N23/52

CPC分类号： H01L24/05 , H01L24/08 , H01L24/16 , H01L2224/0401 , H01L2224/05557 , H01L2224/0807 , H01L2224/16014 , H01L2224/16227 , H01L2924/3512 , H01L2924/3841

摘要： A pad includes a terminal portion having a first surface and a second surface opposite to the first surface; and a curved concave portion formed in one of the first surface and the second surface, wherein the curved concave portion is configured to clad a portion of a connecting conductor.

3.

发明公开
POWER MODULE 审中-公开

公开(公告)号：US20240321692A1

公开(公告)日：2024-09-26

申请号：US18573297

申请日：2022-06-24

申请人： AMOSENSE CO., LTD.

发明人： Jinhyuck BIN , Hyeonchoon CHO , Taeho CHO , Intae YEO , Ikseong PARK , Seunggon PARK

IPC分类号： H01L23/49 , H01L23/00 , H01L23/373 , H01L25/07

CPC分类号： H01L23/49 , H01L23/3735 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/072 , H01L2224/32225 , H01L2224/48155 , H01L2224/73265 , H01L2924/1033 , H01L2924/30107 , H01L2924/3512

摘要： The present disclosure relates to a power module comprising: a base plate; a ceramic substrate bonded to the top surface of the base plate; a semiconductor chip bonded to the top surface of the ceramic substrate; a spacer bonded to the top surface of the ceramic substrate so as to be spaced apart from the semiconductor chip; a connection pin provided at an electrode layer formed on the top surface of the spacer; and a bonding wire for connecting a terminal of the semiconductor chip to the electrode layer of the spacer.

4.

发明公开
BONDING WIRE FOR SEMICONDUCTOR DEVICES 审中-公开

公开(公告)号：US20240290745A1

公开(公告)日：2024-08-29

申请号：US18572708

申请日：2023-03-23

申请人： NIPPON MICROMETAL CORPORATION

发明人： Daizo ODA , Motoki ETO , Takashi YAMADA , Teruo HAIBARA , Ryo OISHI

IPC分类号： H01L23/00 , G01N23/203 , G01N23/2276

CPC分类号： H01L24/45 , H01L24/43 , H01L24/85 , G01N23/203 , G01N23/2276 , G01N2223/601 , G01N2223/602 , G01N2223/611 , H01L2224/4321 , H01L2224/437 , H01L2224/43825 , H01L2224/43826 , H01L2224/43848 , H01L2224/45147 , H01L2224/45541 , H01L2224/45565 , H01L2224/45644 , H01L2224/45655 , H01L2224/45664 , H01L2224/85035 , H01L2224/85203 , H01L2224/85207 , H01L2924/01005 , H01L2924/01012 , H01L2924/01015 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01034 , H01L2924/01049 , H01L2924/01051 , H01L2924/01052 , H01L2924/3512 , H01L2924/3651

摘要： The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy and a coating layer containing conductive metal other than Cu formed on a surface of the core material. The coating layer has a region containing Ni as a main component on a core material side, and has a region containing Au and Ni on a wire surface side, in a thickness direction of the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, a ratio of a concentration CAu (mass %) of Au to a concentration CNi (mass %) of Ni relative to the entire wire is 0.02

5.

发明公开
BONDING WIRE FOR SEMICONDUCTOR DEVICES 审中-公开

公开(公告)号：US20240290743A1

公开(公告)日：2024-08-29

申请号：US18572127

申请日：2022-03-16

申请人： NIPPON MICROMETAL CORPORATION

发明人： Daizo ODA , Motoki ETO , Takashi YAMADA , Teruo HAIBARA , Ryo OISHI

IPC分类号： H01L23/00 , G01N23/203 , G01N23/2276

CPC分类号： H01L24/45 , H01L24/43 , H01L24/85 , G01N23/203 , G01N23/2276 , G01N2223/601 , G01N2223/602 , G01N2223/611 , H01L2224/4321 , H01L2224/437 , H01L2224/43825 , H01L2224/43848 , H01L2224/45147 , H01L2224/45541 , H01L2224/45565 , H01L2224/45644 , H01L2224/45655 , H01L2224/45664 , H01L2224/85035 , H01L2224/85203 , H01L2224/85207 , H01L2924/01005 , H01L2924/01012 , H01L2924/01015 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01034 , H01L2924/01051 , H01L2924/01052 , H01L2924/3512 , H01L2924/3651

摘要： There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieves a favorable bond reliability of the 2nd bonded part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices is characterized in that the bonding wire includes: a core material of Cu or Cu alloy; and a coating layer containing conductive metal other than Cu formed on a surface of the core material, wherein the coating layer has a region containing Pd as a main component on a core material side, and has a region containing Ni and Pd in a range from a wire surface to a depth of 0.5 d when a thickness of the coating layer is defined as d (nm) in a thickness direction of the coating layer, the thickness d of the coating layer is 10 nm or more and 130 nm or less, a ratio CNi/CPd of a concentration CNi (mass %) of Ni to a concentration CPd (mass %) of Pd relative to the entire wire is 0.02 or more and 0.7 or less, a position indicating a maximum concentration of Ni is present in the range from the wire surface to a depth of 0.5 d in a concentration profile in a depth direction of the wire, and the maximum concentration of Ni is 10 atomic % or more, and at least one of the following conditions (i) and (ii) is satisfied:

(i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less
(ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

6.

发明授权
Method for manufacturing semiconductor package structure 有权

公开(公告)号：US12062590B2

公开(公告)日：2024-08-13

申请号：US16725189

申请日：2019-12-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ting-Yu Yeh , Chia-Hao Hsu , Weiming Chris Chen , Kuo-Chiang Ting , Tu-Hao Yu , Shang-Yun Hou

IPC分类号： H01L23/373 , H01L21/66 , H01L23/00 , H01L27/06

CPC分类号： H01L23/3735 , H01L22/32 , H01L23/562 , H01L24/17 , H01L27/0688 , H01L2924/3511 , H01L2924/3512

摘要： A semiconductor package structure includes a substrate, a first semiconductor and a second semiconductor over the substrate, and a multi-TIM structure disposed over the first semiconductor die and the second semiconductor die. The first semiconductor die includes a first heat output and the second semiconductor die includes a second heat output less than the first heat output. The multi-TIM structure includes a first TIM layer disposed over at least a portion of the first semiconductor die and a second TIM layer. A thermal conductivity of the first TIM layer is higher than a thermal conductivity of the second TIM layer. The first TIM layer covers the first semiconductor die.

7.

发明公开
SEMICONDUCTOR PACKAGE 审中-公开

公开(公告)号：US20240234288A1

公开(公告)日：2024-07-11

申请号：US18384386

申请日：2023-10-27

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/498 , H01L23/00 , H01L23/31 , H01L25/065

CPC分类号： H01L23/49838 , H01L23/3107 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0655 , H01L24/48 , H01L2224/1012 , H01L2224/13017 , H01L2224/13083 , H01L2224/16227 , H01L2224/16238 , H01L2224/48225 , H01L2224/73207 , H01L2924/3512

摘要： Provided is a semiconductor package, and more particularly, a semiconductor package in which a semiconductor device is protected in such a way that stress from push and thermal expansion generated while molding by a package housing is dispersed or absorbed through an electrical connecting member having a non-vertical structure bent in a z-letter shape.

8.

发明授权
Warpage control of semiconductor die 有权

公开(公告)号：US12021002B2

公开(公告)日：2024-06-25

申请号：US17884286

申请日：2022-08-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yun-Ting Wang , Yi-An Lin , Ching-Chuan Chang , Po-Chang Kuo

IPC分类号： H01L23/31 , H01L21/02 , H01L21/56 , H01L23/00 , H01L23/29

CPC分类号： H01L23/3171 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/563 , H01L23/291 , H01L23/3192 , H01L24/09 , H01L24/17 , H01L2224/0401 , H01L2924/3511 , H01L2924/3512

摘要： A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

9.

发明公开
HANDLING A FRAGILE SUBSTRATE FOR INTERCONNECT BONDING 审中-公开

公开(公告)号：US20240194634A1

公开(公告)日：2024-06-13

申请号：US18078163

申请日：2022-12-09

申请人： ASMPT SINGAPORE PTE. LTD.

发明人： Keng Yew SONG , Yue ZHANG , Kim Heng TAN

IPC分类号： H01L23/00

CPC分类号： H01L24/78 , H01L24/75 , H01L24/81 , H01L24/85 , H01L2224/751 , H01L2224/75251 , H01L2224/7565 , H01L2224/75802 , H01L2224/75804 , H01L2224/75981 , H01L2224/781 , H01L2224/78251 , H01L2224/7865 , H01L2224/78802 , H01L2224/78804 , H01L2224/78981 , H01L2224/8109 , H01L2224/81093 , H01L2224/81097 , H01L2224/81203 , H01L2224/8509 , H01L2224/85093 , H01L2224/85097 , H01L2224/85203 , H01L2924/3511 , H01L2924/3512

摘要： A bonding apparatus has a bonding platform including a top plate for supporting a fragile semiconductor substrate during interconnect bonding operations conducted on the substrate. Vacuum holes situated on the top plate, forming a first vacuum section, a second vacuum section, and a third vacuum section located between the first and second vacuum sections, generate vacuum suction forces on the substrate during bonding. Individually controllable first, second and third vacuum supplies are connected to the first, second and third vacuum sections respectively. The first and second vacuum supplies cooperate at a first bonding position to generate a vacuum suction force at the first and second vacuum sections, and the second and third vacuum supplies cooperate at a second bonding to position to generate a vacuum suction force at the second and third vacuum sections.