公开(公告)号：US20240164091A1

公开(公告)日：2024-05-16

申请号：US18322842

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub Kim ,  Chung Jin Kim ,  Hyungang Kim ,  Soyeon Seok ,  Jungho Lee ,  Yunkyu Jung

IPC: H10B41/27 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506 ,  H01L2225/06524

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a source structure that includes a support source layer, a gate stack structure on the support source layer, a memory channel structure that penetrates through the gate stack structure and the support source layer, and a separation structure that penetrates through the gate stack structure and the support source layer. The support source layer includes a first source part through which the memory channel structure penetrates, and a second source part through which the separation structure penetrates. A top surface of the first source part is at a level lower than that of a top surface of the second source part.

公开(公告)号：US12144171B2

公开(公告)日：2024-11-12

申请号：US17557642

申请日：2021-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub Kim ,  Dongmin Kyeon ,  Hayan Park ,  Youngsun Cho ,  Changhyun Hur

IPC: H10B41/41 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure on the source structure, the gate stack structure including a word line, a gate upper line and a staircase structure, a memory channel structure and a dummy channel structure extending through the gate stack structure, a cut structure extending through the gate upper line, and a bit line overlapping with the memory channel structure. The cut structure includes a narrow section, and a wide section nearer to the staircase structure than the narrow section. A width of the narrow section is less than a width of the wide section.

公开(公告)号：US20220392911A1

公开(公告)日：2022-12-08

申请号：US17557642

申请日：2021-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choasub Kim ,  Dongmin Kyeon ,  Hayan Park ,  Youngsun Cho ,  Changhyun Hur

IPC: H01L27/11529 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure on the source structure, the gate stack structure including a word line, a gate upper line and a staircase structure, a memory channel structure and a dummy channel structure extending through the gate stack structure, a cut structure extending through the gate upper line, and a bit line overlapping with the memory channel structure. The cut structure includes a narrow section, and a wide section nearer to the staircase structure than the narrow section. A width of the narrow section is less than a width of the wide section.