公开(公告)号：US20200168611A1

公开(公告)日：2020-05-28

申请号：US16566510

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyeon Jeon ,  Se-keun Park ,  Dong-sik Park ,  Seok-ho Shin

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L21/306

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

公开(公告)号：US11177264B2

公开(公告)日：2021-11-16

申请号：US16566510

申请日：2019-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hyeon Jeon ,  Se-keun Park ,  Dong-sik Park ,  Seok-ho Shin

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/28

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

公开(公告)号：US20230039205A1

公开(公告)日：2023-02-09

申请号：US17723747

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Woo Jang ,  Dong-Wan Kim ,  Keonhee Park ,  Dong-sik Park ,  Joonsuk Park ,  Jihoon Chang

IPC: H01L27/108

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.