ELECTRONIC APPARATUS AND CONTROLLING METHOD THEREOF

    公开(公告)号:US20240347169A1

    公开(公告)日:2024-10-17

    申请号:US18594639

    申请日:2024-03-04

    CPC classification number: G16H20/60

    Abstract: An electronic apparatus and a controlling method thereof are provided. The electronic apparatus includes memory storing one or more computer programs, and one or more processors communicatively coupled to the memory, wherein the one or more computer programs include computer-executable instructions executed by the one or more processors and wherein the one or more processors configured to acquire nutritional ingredient information corresponding to food information in case of acquiring the food information, acquire candidate food probability information based on the nutritional ingredient information, and acquire final food group capacity information corresponding to the food information based on the nutritional ingredient information and the candidate food probability information.

    SEMICONDUCTOR DEVICE
    2.
    发明申请

    公开(公告)号:US20220122894A1

    公开(公告)日:2022-04-21

    申请号:US17567403

    申请日:2022-01-03

    Abstract: A method for manufacturing a semiconductor device includes forming a first active fin and a second active fin on a first active region and a second active region of a substrate, respectively, forming a device isolation layer to cover sidewalls of lower portions of the first active fin and the second active fin, forming a first liner layer and a second liner layer to cover upper portions of the first active fin and the second active fin, respectively, forming a first gate electrode and a second gate electrode on the first active fin and the second active fin, respectively, and forming a first source/drain region and a second source/drain region on the first active fin and the second active fin, respectively. The first liner layer includes a different material from a material of the second liner layer.

    INTEGRATED CIRCUIT DEVICES
    4.
    发明申请

    公开(公告)号:US20220208965A1

    公开(公告)日:2022-06-30

    申请号:US17379051

    申请日:2021-07-19

    Abstract: An integrated circuit device includes: a fin-type active region on a substrate and including a fin top surface at a first level; a gate line on the fin-type active region; and an insulating structure on a sidewall of the fin-type active region. The insulating structure includes: a first insulating liner in contact with a sidewall of the fin-type active region; a second insulating liner on the first insulating liner and including an uppermost portion at a second level c than the first level; a lower buried insulating layer facing the sidewall of the fin-type active region and including a first top surface facing the gate line at a third level lower than the second level; and an upper buried insulating layer between the lower buried insulating layer and the gate line and including a second top surface at a fourth level equal to or higher than the second level.

    SEMICONDUCTOR DEVICE
    5.
    发明申请

    公开(公告)号:US20200185280A1

    公开(公告)日:2020-06-11

    申请号:US16793997

    申请日:2020-02-18

    Abstract: A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.

    SEMICONDUCTOR DEVICES
    6.
    发明申请

    公开(公告)号:US20230059177A1

    公开(公告)日:2023-02-23

    申请号:US17720571

    申请日:2022-04-14

    Abstract: A semiconductor device including a first conductive layer on a substrate, a second conductive layer on the first conductive layer, a contact structure between the first and second conductive layers, and a barrier structure surrounding a lower region of a side surface of the second conductive layer, wherein the contact structure includes a contact conductive layer having a first upper surface portion and a second upper surface extending from the first upper surface portion and being concave, and a gap-fill pattern fills a space between the second upper surface portion and the second conductive layer and includes a first gap-fill insulating layer including a metal element and a second gap-fill insulating layer including a silicon element, and the barrier structure includes a first etch stop layer and a barrier layer that include same materials as the first insulating material and the second insulating material, respectively, may be provided.

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