公开(公告)号：US12009274B2

公开(公告)日：2024-06-11

申请号：US17358149

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eungkyu Kim ,  Kyounglim Suk

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/367 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

公开(公告)号：US20240128155A1

公开(公告)日：2024-04-18

申请号：US18379841

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Bae ,  Eungkyu Kim ,  Jongyoun Kim

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/3738 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0655 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: Provided is a semiconductor package comprising a redistribution structure including a redistribution pattern and a redistribution insulation layer covering the redistribution pattern, a semiconductor chip disposed on the redistribution structure and having an active surface and an inactive surface opposite to the active surface, a molding layer disposed on the redistribution structure and covering at least a portion of the semiconductor chip, and a silicon heat dissipation structure disposed on the semiconductor chip, wherein the silicon heat dissipation structure is bonded to the semiconductor chip through silicon (Si)-to-Si direct bonding.

公开(公告)号：US11646260B2

公开(公告)日：2023-05-09

申请号：US17206291

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/1355 ,  H01L2224/13541 ,  H01L2224/1607 ,  H01L2224/16013 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US11508649B2

公开(公告)日：2022-11-22

申请号：US17222912

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eungkyu Kim ,  Jongyoun Kim ,  Gwangjae Jeon

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.

公开(公告)号：US11929316B2

公开(公告)日：2024-03-12

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Eungkyu Kim ,  Gwangjae Jeon

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/13016 ,  H01L2224/13541 ,  H01L2224/1355 ,  H01L2224/16013 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17055 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/81345 ,  H01L2224/81815

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20240006262A1

公开(公告)日：2024-01-04

申请号：US18176695

申请日：2023-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Eungkyu Kim ,  Hyeonseok Lee

IPC: H01L23/367 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L23/3677 ,  H01L25/165 ,  H10B80/00 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3738 ,  H01L24/16

Abstract: A semiconductor package includes a first redistribution structure, a first die above the first redistribution structure, a second die above the first die, a heat dissipation unit on side surfaces of the first die or the second die, and a second redistribution structure above the second die. The semiconductor package includes a first post protruding from an upper surface of the first redistribution structure and extending to a lower surface of the second redistribution structure, a second post connecting the heat dissipation unit with a heat dissipation redistribution structure as a thermal path, and a molding unit filling an empty space between the first redistribution structure and the second redistribution structure. An outer pad of the heat dissipation redistribution structure is exposed to an outside of the semiconductor package, and an inner pad of the heat dissipation redistribution structure is in contact with the second post.