公开(公告)号：US20220246837A1

公开(公告)日：2022-08-04

申请号：US17486034

申请日：2021-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kil Ho Lee ,  Gwan Hyeob Koh ,  Yong Jae Kim ,  Geon Hee Bae

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetic memory device includes a substrate having a first mold insulating film on a first region thereof, and a first structure on the substrate. The first structure includes a lower electrode, a magnetic tunnel junction (MTJ) structure on the lower electrode, and an upper electrode on the MTJ structure. A capping film is provided, which extends on the first mold insulating film and sidewalls of the first structure. A first etching stop layer is provided on the first structure and the capping film. A second mold insulating film is provided, which at least partially fills a space between the capping film and the first etching stop layer. A first metal structure is provided, which extends through a portion of the first etching stop layer and a portion of the second mold insulating film, and is electrically coupled to the MTJ structure.

公开(公告)号：US20230371276A1

公开(公告)日：2023-11-16

申请号：US18156570

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geon Hee Bae ,  Seung Pil Ko ,  Yoon Jong Song ,  Kil Ho Lee

IPC: H10B61/00

CPC classification number: H10B61/00 ,  G11C11/1673

Abstract: A magnetic memory device includes first and second upper insulating layers and a first mold layer sequentially stacked on a first substrate region; a first primary and first secondary wiring structure spaced apart in a first direction in the first upper insulating layer; a second wiring structure on the first primary wiring structure and a reference wiring structure on the first secondary wiring structure, in the second upper insulating layer; a first structure on the second wiring structure; a second structure on the reference wiring structure; a lower electrode contact between the second wiring structure and the first structure, and not between the reference wiring structure and the second structure, in the first mold layer; a bit line structure on the first structure; and a reference bit line structure on the second structure. The first and second structure include a lower electrode, MTJ structure, intermediate electrode, and upper electrode.