公开(公告)号：US12022744B2

公开(公告)日：2024-06-25

申请号：US17469502

申请日：2021-09-08

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Koog Kim ,  Jae Hak Yang ,  Yoon Jong Song ,  Kil Ho Lee ,  Jun Hoe Kim

IPC: H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/80 ,  H10N52/00

CPC classification number: H10N50/85 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3286 ,  H10B61/00 ,  H10N50/80 ,  H10N52/00

Abstract: A core magnetization reversal method includes transforming the first magnetic skyrmion into a skyrmionium by applying a first alternating current (AC) magnetic field to the first magnetic skyrmion, and then transforming the skyrmionium into a second magnetic skyrmion by applying a second AC magnetic field to the skyrmionium. The first magnetic skyrmion may be formed on a hemispherical shell, which may be formed by (i) preparing a membrane having a plurality of protrusions, and (ii) stacking, on the membrane, a first layer including at least one of platinum (Pt), nickel (Ni), and palladium (Pd), and a second layer including a ferromagnetic material. The first and second AC magnetic fields may have different frequencies.

公开(公告)号：US20230371276A1

公开(公告)日：2023-11-16

申请号：US18156570

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geon Hee Bae ,  Seung Pil Ko ,  Yoon Jong Song ,  Kil Ho Lee

IPC: H10B61/00

CPC classification number: H10B61/00 ,  G11C11/1673

Abstract: A magnetic memory device includes first and second upper insulating layers and a first mold layer sequentially stacked on a first substrate region; a first primary and first secondary wiring structure spaced apart in a first direction in the first upper insulating layer; a second wiring structure on the first primary wiring structure and a reference wiring structure on the first secondary wiring structure, in the second upper insulating layer; a first structure on the second wiring structure; a second structure on the reference wiring structure; a lower electrode contact between the second wiring structure and the first structure, and not between the reference wiring structure and the second structure, in the first mold layer; a bit line structure on the first structure; and a reference bit line structure on the second structure. The first and second structure include a lower electrode, MTJ structure, intermediate electrode, and upper electrode.