公开(公告)号：US20250133793A1

公开(公告)日：2025-04-24

申请号：US18663416

申请日：2024-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryeol YOO ,  Jaejun KIM ,  Ingyu JANG ,  Gwangjun KIM ,  Sunghwan KIM ,  Jiwon JEONG ,  Jeongsang PYO

IPC: H01L29/36 ,  H01L29/167

Abstract: A semiconductor device includes a substrate; an active pattern extending on the substrate in a first direction; a plurality of channel layers on the active pattern and spaced apart from each other in a vertical direction; a gate structure crossing the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction orthogonal to the first direction; and source/drain patterns on a region of the active pattern on both sides of the gate structure, and having a semiconductor liner layer connected to each of side surfaces of the plurality of channel layers, and a semiconductor filling layer on the semiconductor liner layer. The semiconductor liner layer includes silicon-germanium (SiGe) doped with a first conductivity-type impurity. The semiconductor filling layer includes an epitaxial layer having a germanium (Ge) concentration higher than that of the semiconductor liner layer, and the epitaxial layer is doped with Ga.

公开(公告)号：US20240088219A1

公开(公告)日：2024-03-14

申请号：US18452858

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pilkwang KIM ,  Seunghyun SONG ,  Yoonsuk KIM ,  Gwangjun KIM ,  Jaemin KIM

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.