公开(公告)号：US20190304991A1

公开(公告)日：2019-10-03

申请号：US16243236

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun SEO ,  Hyun-Seok NA ,  Heejueng Lee ,  Heung Jin Joo

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L29/06

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.

公开(公告)号：US10937797B2

公开(公告)日：2021-03-02

申请号：US16243236

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjun Seo ,  Hyun-Seok Na ,  Heejueng Lee ,  Heung Jin Joo

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L29/06 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11565

Abstract: A three-dimensional semiconductor memory device may include a substrate including a cell array region, a peripheral circuit region, and a connection region between the cell array region and the peripheral circuit region. The memory device may include an electrode structure extending from the cell array region toward the connection region and comprising electrodes stacked on the substrate, a horizontal gate dielectric layer between the electrode structure and the substrate and including a first portion on the cell array region and a second portion on the connection region, the second portion thicker than the first portion in the vertical direction, first vertical channels on the cell array region and penetrating the electrode structure and the first portion of the horizontal gate dielectric layer, and second vertical channels on the connection region and penetrating the electrode structure and the second portion of the horizontal gate dielectric layer.